Raster I is a hardware renderer that specializes in real-time rasterization and is based on the Tile-Based Deferred Rendering (TBDR) architecture. Currently, several crucial features are implemented along with a tiled Pineda style rasterizer, including hardware-accelerated transform and lighting (T&L), deferred Phong shading, double buffering, VSync, MSAA anti-aliasing, ordered dithering and back-face culling. Its implementation is divided into two parts, one is written in Chisel HDL, and the other is based on Xilinx Vitis HLS.

Furthermore, Raster I consists of a multi-cycle vertex transformer, 8 parallel interpolator pipelines, and a deferred shading pipeline that employs the Phong shading model (internal calculations use Q11.13 fixed point numbers). The output VGA signal can be configured up to 1024x768 @ 60Hz, and tiles of size 64x32 are rendered sequentially. Visual enhancements are also supported with minimal overhead, such as ordered dithering for displaying pseudo 24bpp pixels and MSAA 4x anti-aliasing. If there is enough BRAM left over for texture storage, an optional texture sampling unit is also available.

As a result, this GPU utilizes 69% LUT, 97% BRAM, and 88% DSP from Digilent Arty A7-100T and can render a 3D model with 3K faces at a screen resolution of 1024x768 and a clock frequency of 100MHz at about 30FPS. It is also worth mentioning that this is only the first iteration of Project Raster, with key features like GPGPU ISA yet to be implemented. Therefore, in future releases, it will eventually evolve into a fully-fledged open-source hardware that supports practically all of the typical features of modern GPUs.

The architecture of Raster I can be mainly viewed as 3 clock domains: system, graphics and display (their frequencies are currently 100MHz, 100MHz and 65MHz). While the components in the graphics clock domain is responsible for executing traditional rendering processes, the display clock domain is in charge of reading the framebuffer in DRAM, applying effects like dithering and putting it onto the screen synchronously. At the heart of the system, there sits a framebuffer swapper which behaves as a coordinator between the graphics and display clock domains.