Talk:Skylake (microarchitecture)

Reliability of Source "SemiAccurate"

All of the information seems to have originated from SemiAccurate, which is described as a "satire" site. Moreover, the original article was posted on April Fools' Day, which makes it even more suspect. Can this be verified through another source? --Ixfd64 (talk) 16:07, 2 May 2011 (UTC)

I wouldn't call SemiAccurate a satire site. Anyway, here's another source: http://www.h-online.com/newsticker/news/item/Processor-Whispers-Of-dear-friends-and-engravers-1263024.html. It reports: "In any case, the Haswell successors have already been named: Broadwell with a reduction (shrink) to 14 nm (P1272) and then Skylake with a new microarchitecture – probably again from Haifa – a decrease to 11 nm version (p1274) which is scheduled to roll out as Skymont in 2015." Note that it reports 11 nm for Skymont's feature size, although the Intel slides (reference 2) report 10nm. (probably 10 nm then. Marc Bohr, Intel Senior Fellow ought to be right about this.) Also note that it's a bit unclearly written - Skylake will be a new microarchitecture on the 14 nm process that was introduced with Broadwell. — Preceding unsigned comment added by 89.150.76.19 (talk) 11:26, 6 December 2011 (UTC)

The successor to Skylake is actually Cannonlake Echrei (talk) 18:37, 2 January 2012 (UTC)

If you have a reliable source for this name change, we should move this article there. -XJDHDR (talk) 15:10, 1 June 2012 (UTC)

What if all the public sources are wrong? — Echrei (talk • contribs) 20:25, 10 July 2012 (UTC)

I can actually confirm as well that it's not called Skymont. The info needs to be removed for lack of sources, and any sources used won't be solid enough, because I know for a fact they'd be wrong calling it Skymont. I won't say what the real name is, but the product is so far off that the name is still subject to change. Skylake is the farthest out that any resources are being committed, so far as I know.— Preceding unsigned comment added by 72.222.181.94 (talk) 07:21, 8 September 2012 (UTC)

72.222.181.94

2403:6200:8833:60C8:2CB1:A1C9:F722:B4B(พูด)23:43,

9 เมษายน 2024 (UTC)

2403:6200:8833:60C8:2CB1:A1C9:F722:B4B (talk) 23:46, 9 April 2024 (UTC)

Dubious

A die shrink would not conform with "tick-tock", where Skymont would be a new die at the same size. -lysdexia 03:20, 13 June 2012 (UTC) — Preceding unsigned comment added by 99.64.168.136 (talk)

Your comprehension of tick-tock seems a bit off. It's a new design on an existing process (tick) followed by that design on a new process (tock.) Skylake is the tick (uses a new design, but the same 14nm process as Broadwell) while Skymont is the tock (Skylake core shrunk to 10nm.) Kiralexis (talk) 00:37, 24 June 2012 (UTC)

This is correct. Skylake is the new design on same process, and Skymont is the shrink. Taylor (talk) 20:34, 24 June 2012 (UTC)

140427 Broadwell (?4q14) will be the 14nm die shrink of the 22nm Haswell new microarchitecture (2q13). e.g. i7 Nehalem 45nm 4q08, die shrink into Westmere 32nm 1q10; Sandy Bridge 32nm 1q11 new architecture was die shrunk into Ivy Bridge 22nm 3q11.

Therefore Skylake (?2016) should be a new microarchitecture. Intel "classified" Cannonlake at 10nm will be the die shrink of 14nm Skylake. "classified" as Intel is not willing to publically divulge the actual semiconductor it will be using to replace the curent Silicon base material in cpu due to r&d outlays. Bhug (talk) 21:47, 27 April 2014 (UTC)

Intel slides on "Seeking Alpha"

In this article: http://seekingalpha.com/article/1529392-intel-s-skylake-is-a-monster (free registration required to read the whole thing) the author shows pieces of what look like real Intel slides. Among other things, the article claims specific feature details of Skylake such as "SSE3.2" (allegedly being a little better than the SSE in Xeon Phi, that is, a 512-bit-wide vector unit), DDR4 (also listed under Haswell), and PCI Express 4.0.

I traced the source to here: http://wccftech.com/intel-14nm-skylake-processors-feature-pcie-4-ddr4-memory-sata-express/ and here: http://www.madboxpc.com/intel-skylake-soportara-memorias-ddr4-pcie-4-0-avx-3-2-sata-express-y-14nm/ and here: http://www.pcgameshardware.de/CPU-Hardware-154106/News/Skylake-Intel-14-nm-PCI-E-4-DDR4-SATA-Express-1076762/ and finally here: http://www.icsr.agh.edu.pl/~kito/Arch/arch1-1-4B-x86.pdf

Also included in these articles is a claim that Skylake will have "SATA Express".

I consider all of these suspect. In particular, the PDF file at www.icsr.agh.edu.pl has a lot of slides from different Intel presentations over the years, plus some slides that seem to have been created as collages from other material, and slides in Polish (presumably the language of the person creating the compilation). I'd want to trace the "Intel slides" with Skylake info to actual Intel PDFs.

So can we use any of these sources?

Broadwell canceled

Because Broadwell is canceled and replaced with a Haswell refresh, Broadwell should be removed from the diagram. — Preceding unsigned comment added by 84.82.64.201 (talk) 19:56, 21 July 2013 (UTC)

Broadwell was never cancelled. There was talk of Broadwell not coming to the desktop, but it was always planned for mobile. The desktop would only get a Haswell refresh. But at the moment, it looks like Intel revised their plans, and that there is indeed at least a Broadwell K coming to the desktop. — Preceding unsigned comment added by 5.103.47.116 (talk) 10:20, 22 January 2014 (UTC)

Caches

Am I the only one who doubts the accuracy of the listed cache specifications?

Currently listed for Skylake:

• 128 KB L1 cache (64 KB 16-way set associative instruction cache + 64 KB 16-way set associative data cache) (2 cycles)
• 512 KB L2 cache, 16-way set associative (6 cycles)
• 12 MB L3 cache, 24-way set associative (12 cycles)

It looks very specific, and it's mainly the latencies that make me suspicious. Doubling the caches and cutting latencies in half at the same time? (See Haswell data below). Usually, larger memories have larger latencies, and the requirement of low latencies is as far as I know the main reason that the lower level caches have to be kept small. Also, there are no citations, it doesn't seem to be published anywhere else, and we have had people listing doubling of the caches for Haswell without citation, which didn't happen, as well.

Haswell, according to http://agner.org/optimize/microarchitecture.pdf, page 142:

• 64 KB L1 cache (32 KB 8-way set associative instruction cache + 32 KB 8-way set associative data cache) (4 cycles)
• 256 KB L2 cache, 8-way set associative (11 cycles)
• 8 MB L3 cache, 16-way set associative (33? cycles) — Preceding unsigned comment added by 5.103.47.116 (talk) 11:23, 22 January 2014 (UTC)

Hello there! Anyway, more references are required for this article, which is basically still a collection of rumors and it's based on leaked materials; actually released product, of course, could be significantly different. — Dsimic (talk) 13:11, 23 January 2014 (UTC)

apple A7, Z-360, Sparc. PowerPC and AMD's athlon managed to reduce their latency on while kept the decent size of the L1 cache. especially AMD able to keep 3 cycle on their 128kb cache while only have 2 way set associativity. I don't see why not on intel's case. especially AVX has extend to 512 bit and L1 cache became bottleneck. like SSE was bottleneck on netburst and pentium III which was why Intel increase the size from 8~16KB to 32+32kb.

I've been glad to see that this was removed by a reader from realworldtech.com (including Linus Torvalds, who agreed it had to be total nonsense), after a short discussion there. According to that person, the original source was a known vandal who had also vandalized a number of other pages. I'd like to see large caches on Skylake, but we will have to see what Intel come out with... — Preceding unsigned comment added by 5.103.75.44 (talk) 10:39, 22 October 2014 (UTC)

Information on precise cycles measuring

Tom Forsyth, a former Intel employee, stated in his presentation on slide 30 that:

 Hardware configuration problems - Clocks
  - Precise CPU clock measures cycles 
    * Finally fixed with Skylake CPUs – reliable AND precise
    * But Skylake isn’t out yet…

I thing this is a very interesting news, which might interest the great number of readers, but I'm not under which section could this be at article page, or is this even an enough confirmation to present it. --217.67.201.162 (talk) 13:19, 12 February 2015 (UTC)

Hello! I'd suffest that, for now, we add that presentation into the "External links" section. Hope you agree. — Dsimic (talk | contribs) 01:26, 17 February 2015 (UTC)

Kaby Lake

It seems that all of the Kaby Lake info is based on a supposedly leaked slide released by one site (Benchlife.info). What are thoughts on removing the Kaby Lake link from successors until there is some reputable, verifiable information out there? I don't feel like rumors have a place on a Wikipedia page, even if they do turn out to be true. — Preceding unsigned comment added by 12.156.158.3 (talk) 13:09, 26 June 2015 (UTC)

Totally agreed, we should wait with the Kaby Lake until the roadmap is officially confirmed; currently, it seems that Intel hasn't confirmed it yet. — Dsimic (talk | contribs) 17:53, 8 July 2015 (UTC)

Kaby Lake appears to be now confirmed. But Ice Lake replacing Cannonlake as far as I can see is not confirmed; CEO referred to Cannonlake as of the July 16th earnings call. — Preceding unsigned comment added by 27.252.66.137 (talk) 02:41, 21 July 2015 (UTC)

Skylake-S list (1st Septemter, 2015)

I was create sheet of all released models (from i7 to Pentium) from official sources and Anandtech article [1]. But I don't have enough experiences to fill large merged columns on Wikipedia - it's still too complicated for me. I propose to use same type of table that used on Haswell https://en.wikipedia.org/wiki/Haswell_%28microarchitecture%29#Desktop_processors

Here is my shared (read-only) folder with Excel online sheet http://1drv.ms/1i2TvdA

Skylake also support power efficient DDR3L-RS. — Preceding unsigned comment added by JanCerny-HoNY (talk • contribs) 02:15, 5 September 2015 (UTC)

btw: Intel NDA for Skylake was ended on 1st September, 2015 9 PM PDT, but Skylake-Y/U/H/S CPUs was launched on 2nd September 2015 at IFA Berlin 2015 [2]. — Preceding unsigned comment added by JanCerny-HoNY (talk • contribs) 02:08, 5 September 2015 (UTC)

processors have wrong clock g4400 runs slower g4400t is missing g4500t or so is also missing, any t ending cpu is missing — Preceding unsigned comment added by 194.166.124.217 (talk) 08:13, 30 September 2015 (UTC)

Xeon E3 V5 do *NOT* have AVX-512.

The ARK pages say so. The current article makes it as if all Skylake Xeon come with AVX-512, which is false. 111.196.74.130 (talk) 16:09, 14 December 2015 (UTC)

Core M

The "Core M" redirect seems inappropriate. "Core M" redirects to this page on Skylake and "Core-M" redirects to Broadwell_(microarchitecture). Core M is a branding beyond both Skylake and Broadwell. "Core M" may be a topic large enough to warrant its own page, but until someone creates that, changing the redirect to the List_of_Intel_Core_M_microprocessors would be an improvement since at least it includes a summary of what is meant by "Core M". 156.143.240.137 (talk) 20:33, 7 January 2016 (UTC)

New Skylake Celeron desktop processors

These are now on ARK - G3900 and G3900T. I don't know how to put them on, if someone could oblige? thanks

Bug?

Should this be noted? Intel has confirmed a bug in some Skylake CPUs could cause them to lock up under “complex workload conditions” but noted that a fix is on the way, PCWorld Jan 11, 2016 1:19 PM.Tom Ruen (talk) 07:07, 20 January 2016 (UTC)

In my opinion, yes. Multiple reliable sources have already reported on this. -- Chamith (talk) 08:26, 20 January 2016 (UTC)

L4 cache

Because Skylake brings a range of possibilities for L4 cache (none, 64MB, or 128MB), I've added an "L4 cache" column after the L3 cache column in the mobile processor list. I'll add it to the remaining lists soon. 184.75.221.3 (talk) 18:51, 24 January 2016 (UTC)

I added it to the desktop CPUs list as well. They're all "N/A" for the time being, which illustrates to readers that none of the current deskop models have L4 cache, but this column is valuable to have in case Intel announces desktop CPUs with L4 cache in the future. 184.75.221.3 (talk) 19:02, 24 January 2016 (UTC)

The skylake table is not accurate anymore -> new cpu i7-6660 replaces i7-6650

The skylake table is not accurate anymore -> new cpu i7-6660 replaces i7-6650 Source: http://www.digitaltrends.com/computing/intel-skylake-processor/ — Preceding unsigned comment added by 78.23.158.33 (talk) 13:11, 8 April 2016 (UTC)

8 core processors is missing from the list

i was shown at least one 8 core skylake processor on komplett.no but that have been removed from the site after that. i therefore do not have any details. 84.212.73.96 (talk) 16:25, 22 June 2016 (UTC)

Move discussion in progress

There is a move discussion in progress on Talk:Haswell (CPU) which affects this page. Please participate on that page and not in this talk page section. Thank you. —RMCD bot 05:32, 11 February 2017 (UTC)

The "CPU turbo clock rate" on Skylake-X is AGAIN wrong

The turbo frecuency (aka single thread turbo clock rate) announced for Skylake-X by Intel were:

7800X - 4.0GHz 7820X/7900X - 4.5 Ghz. 7920X/7940X/7960X/7980XE - 4.4Ghz.

Yet the table is again wrong, with random lower values than that, totally unsourced, also with "dual core" and "quad core" turbo speeds totally unsourced for yet unreleased devices. All that info should be deleted until properly sourced, otherwise the table is useless as it is now.

In fact, the colums need serious reworking, for example, Turbo Boost 2.0 And Turbo Boost 3.0 aren't the same thing. 7960XE has Turbo Boost 2.0 4.2Ghz with 2 cores active, and Turbo Boost 3.0 Max of 4.4 Ghz as sourced by Intel originally. Source for this data: http://www.tomshardware.com/reviews/intel-core-i9-7960x-cpu-skylake-x,5238.html . So the colums need to diferentiate Turbo Boost 2.0 and Turbo Boost 3.0, and then diferentiate by active core count.

Newer Xeons

Just remembered the new Xeons (designated by medal scheme) haven't been added yet.--Azul120 (talk) 23:26, 4 October 2017 (UTC)

Bold

Why are some CPUs written bold in the table? 85.140.228.223 (talk) 13:03, 1 May 2018 (UTC)

I guess it means "popular items" like in the Kaby Lake article.

• Broadwell: all CPUs with external link (Intel ARK)
• Kaby Lake: It states "popular items".
• Coffee Lake: CPUs with unlocked multiplier (overclockable)

— Pizzahut2 (talk) 20:35, 14 May 2018 (UTC)

PAUSE instruction latency issues

FYI - https://aloiskraus.wordpress.com/2018/06/16/why-skylakex-cpus-are-sometimes-50-slower-how-intel-has-broken-existing-code/ • Sbmeirow • Talk • 12:34, 18 June 2018 (UTC)

I've added it here: Skylake (microarchitecture)#Known issues. — Pizzahut2 (talk) 13:39, 18 June 2018 (UTC)

Separated mainstream/high-end CPU tables

I created two new table for the high-end CPUs from the 7th and 9th generations, as the current combined mainstream/HEDT table was getting a bit too cluttered, and adding the 9th generation chips would have been a whole new headache. If someone can find the launch dates for the SKL-X-R parts and their MSRPs (rather than RCP 1k prices? Maybe these are the prices we use, but I don't want to add them unless there's confirmation), please do add them. I've listed them as TBA. ATMarsden^Talk 21:48, 27 October 2018 (UTC)

Quality

François Piednoël, a former Intel engineer, has gone on the record saying "The quality assurance in Skylake was abnormally bad." adding "We were getting way too much citing for little things, and basically Apple became the number-one filer of problems with the architecture. And that went really, really bad. When your customer starts finding almost as much bugs as you found yourself, you're not leading into the right place." (Ex-Intel engineer: Apple turned away from Intel over Skylake CPU bugs ZDNet)--174.99.238.22 (talk) 02:11, 20 October 2020 (UTC)

Split proposal

I propose that this article be split into two: one for the microprocessor family and another for the microarchitecture itself. I think we should split it because:

• Unlike previous microarchitectures, Skylake is the microarch that is in skylake and succeeding "lakes". By having articles for the two, we can distuingish the microprocessor family and the microarch,
• By splitting, it follows the convention set by other articles (Penryn (microarchitecture) and Penryn (microprocessor), Sunny Cove and Ice Lake, Willow Cove and Tiger Lake, Golden Cove and Alder Lake, etc.)

Itsquietuptown t • c 11:55, 10 April 2021 (UTC)

« I propose that this article be split into two: one for the microprocessor family and another for the microarchitecture itself. » => Why not. I already did that in Wikidata. Visite fortuitement prolongée (talk) 07:07, 11 April 2021 (UTC)

« Unlike previous microarchitectures » => Wrong. This was the same for all microarchitectures using the Tick–tock model. Visite fortuitement prolongée (talk) 07:07, 11 April 2021 (UTC)

« Penryn (microarchitecture) and Penryn (microprocessor) » => Wrong example. Penryn (microprocessor) is one microprocessor of the Penryn microprocessor family which use the Intel Core (microarchitecture). Visite fortuitement prolongée (talk) 07:07, 11 April 2021 (UTC)

@Visite fortuitement prolongée: Oh, thanks for replying! I'm really confused by intel's codenames pre-Skylake so thanks for the clarification. Itsquietuptown t • c 03:25, 12 April 2021 (UTC)

@Itsquietuptown: Maybe looking at Template:Intel processor roadmap (which is not perfect) could help you about intel's codenames. Visite fortuitement prolongée (talk) 13:37, 20 May 2021 (UTC)

Shoot, I mean, I agree. Artem S. Tashkinov (talk) 18:15, 9 May 2021 (UTC)

MSRP/Price column discussion

The table seems like largely unsourced trivia to me. The release price (date makes some sense) is irrelevant. We don't post release prices of games or other products as a general matter, especially for something sold worldwide. It seems silly to waste time making conversions to calculate the prices in inflation-adjusted terms or based in other currencies precisely because it's silly. Ricky81682 (talk) 03:35, 4 January 2023 (UTC)

User:Ricky81682 Some CPUs have recommended prices specified, e.g. https://ark.intel.com/content/www/us/en/ark/products/88196/intel-core-i76700-processor-8m-cache-up-to-4-00-ghz.html, so your blanket cleaning of the section/column wasn't the best idea IMO. It's here for at the very least historical purposes to see how much pricing changes year on year. Artem S. Tashkinov (talk) 09:40, 4 January 2023 (UTC)

It is information that is not based on a reliable secondary source. Just because Intel posted it at one point doesn't mean everything needs to be copied here into a table. Is there any reliable secondary source anywhere that discusses historical release prices for CPUs? For these CPUs? And who's historical purposes? People who play with this list and add details? It's trivia. Again, let's compare this to video games, toys, Dell monitors or List of Microsoft Windows versions. There is no mention of "release date price" because it is ridiculous and irrelevant. -- Ricky81682 (talk) 09:54, 4 January 2023 (UTC)

This needs a wider involvement and discussion because pricing is specified in almost all CPU/GPU articles. Either we have it everywhere or nowhere. Historically it's been there. I really don't like that you've edited just a single article and washed your hands off it. Let's invite other editors and reach a consensus.

Speaking of "secondary sources". Wikipedia has never required or needed this because the OEM itself is more than authoritative, so you can trust their data and all other media simply copy this data, so it sounds impossible to find further confirmations or refutations. Etail/retail often has its own markup, then there's been the COVID era, and it all becomes quite murky very fast.

This is English Wikipedia, I'd venture to say it's more oriented towards the citizens of English speaking countries where the US has the largest number of people, so US pricing sounds more than appropriate. Artem S. Tashkinov (talk) 10:14, 4 January 2023 (UTC)

This is the English language Wikipedia, oriented to English speakers worldwide. Speakers of English in the US are a sizeable minority, but still a minority. Dondervogel 2 (talk) 10:54, 4 January 2023 (UTC)

We are still talking about US-based corporations with their domestic MSRP. I don't think it's inappropriate. And again pricing is specified in multiple other articles. Artem S. Tashkinov (talk) 11:11, 4 January 2023 (UTC)

I am not arguing against including price information in principle (I have no opinion on pricing - am open to persuasion). I am arguing against basing the prices on the US market, which leads to the practical question, pointed out by others, of what to use instead. Dondervogel 2 (talk) 11:20, 4 January 2023 (UTC)

Here's an idea. In revised AMD CPUs articles there's MSRP as a column name and it has "US $123" price for items. This looks like it could address your concerns. Artem S. Tashkinov (talk) 12:09, 4 January 2023 (UTC)

« let's compare this to video games, toys, Dell monitors or List of Microsoft Windows versions. There is no mention of "release date price" because it is ridiculous and irrelevant. » => FYI Introductory price in Template:Infobox information appliance, used in Xbox (console), Xbox 360, Xbox One, Xbox Series X and Series S, PlayStation 3, PlayStation 4, PlayStation 5. Visite fortuitement prolongée (talk) 12:41, 4 January 2023 (UTC)

Number of display ports

Intel ARK for the 6875R shows 3 for the number of display ports while only Lenovo and Phoronix shows 5. Subsequent generations of processors support no more than 4 ports. I would suggest that we take the official Intel number of 3. Digital27 (talk) 09:33, 25 November 2023 (UTC)