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For other uses, see CMOS (disambiguation).
CMOS inverter (a NOT logic gate)

Complementary metal–oxide–semiconductor (CMOS, pronounced "sea-moss", /siːmɑːs/, /-ɒs/) is a type of metal–oxide–semiconductor field-effect transistor (MOSFET) fabrication process that uses complementary and symmetrical pairs of p-type and n-type MOSFETs for logic functions.[1] CMOS technology is used for constructing integrated circuit (IC) chips, including microprocessors, microcontrollers, memory chips (including CMOS BIOS), and other digital logic circuits. CMOS technology is also used for analog circuits such as image sensors (CMOS sensors), data converters, RF circuits (RF CMOS), and highly integrated transceivers for many types of communication.

The CMOS process was originally conceived by Frank Wanlass at Fairchild Semiconductor and presented by Wanlass and Chih-Tang Sah at the International Solid-State Circuits Conference in 1963. Wanlass later filed US patent 3,356,858 for CMOS circuitry and it was granted in 1967. RCA commercialized the technology with the trademark "COS-MOS" in the late 1960s, forcing other manufacturers to find another name, leading to "CMOS" becoming the standard name for the technology by the early 1970s. CMOS overtook NMOS as the dominant MOSFET fabrication process for very large-scale integration (VLSI) chips in the 1980s, also replacing earlier transistor–transistor logic (TTL) technology. CMOS has since remained the standard fabrication process for MOSFET semiconductor devices in VLSI chips. As of 2011, 99% of IC chips, including most digital, analog and mixed-signal ICs, were fabricated using CMOS technology.[2]

Two important characteristics of CMOS devices are high noise immunity and low static power consumption.[3] Since one transistor of the MOSFET pair is always off, the series combination draws significant power only momentarily during switching between on and off states. Consequently, CMOS devices do not produce as much waste heat as other forms of logic, like NMOS logic or transistor–transistor logic (TTL), which normally have some standing current even when not changing state. These characteristics allow CMOS to integrate a high density of logic functions on a chip. It was primarily for this reason that CMOS became the most widely used technology to be implemented in VLSI chips.

The phrase "metal–oxide–semiconductor" is a reference to the physical structure of MOS field-effect transistors, having a metal gate electrode placed on top of an oxide insulator, which in turn is on top of a semiconductor material. Aluminium was once used but now the material is polysilicon. Other metal gates have made a comeback with the advent of high-κ dielectric materials in the CMOS process, as announced by IBM and Intel for the 45 nanometer node and smaller sizes.[4]

Technical details

Further information: Semiconductor manufacturing processes

"CMOS" refers to both a particular style of digital circuitry design and the family of processes used to implement that circuitry on integrated circuits (chips). CMOS circuitry dissipates less power than logic families with resistive loads. Since this advantage has increased and grown more important, CMOS processes and variants have come to dominate, thus the vast majority of modern integrated circuit manufacturing is on CMOS processes.[5] CMOS logic consumes around 1/7-th the power of NMOS logic,[6] and about 1/100,000-th the power of bipolar transistor-transistor logic (TTL).[7][8]

CMOS circuits use a combination of p-type and n-type metal–oxide–semiconductor field-effect transistor (MOSFETs) to implement logic gates and other digital circuits. Although CMOS logic can be implemented with discrete devices for demonstrations, commercial CMOS products are integrated circuits composed of up to billions of transistors of both types, on a rectangular piece of silicon of often between 10 and 400 mm2.[citation needed]

CMOS always uses all enhancement-mode MOSFETs (in other words, a zero gate-to-source voltage turns the transistor off).[9]

Inversion

CMOS circuits are constructed in such a way that all P-type metal–oxide–semiconductor (PMOS) transistors must have either an input from the voltage source or from another PMOS transistor. Similarly, all NMOS transistors must have either an input from ground or from another NMOS transistor. The composition of a PMOS transistor creates low resistance between its source and drain contacts when a low gate voltage is applied and high resistance when a high gate voltage is applied. On the other hand, the composition of an NMOS transistor creates high resistance between source and drain when a low gate voltage is applied and low resistance when a high gate voltage is applied. CMOS accomplishes current reduction by complementing every nMOSFET with a pMOSFET and connecting both gates and both drains together. A high voltage on the gates will cause the nMOSFET to conduct and the pMOSFET not to conduct, while a low voltage on the gates causes the reverse. This arrangement greatly reduces power consumption and heat generation. However, during the switching time, both pMOS and nMOS MOSFETs conduct briefly as the gate voltage transitions from one state to another. This induces a brief spike in power consumption and becomes a serious issue at high frequencies.

Static CMOS inverter. Vdd and Vss are standing for drain and source respectively.

The adjacent image shows what happens when an input is connected to both a PMOS transistor (top of diagram) and an NMOS transistor (bottom of diagram). Vdd is some positive voltage connected to a power supply and Vss is ground. A is the input and Q is the output.

When the voltage of A is low (i.e. close to Vss), the NMOS transistor's channel is in a high resistance state, disconnecting Vss from Q. The PMOS transistor's channel is in a low resistance state, connecting Vdd to Q. Q, therefore, registers Vdd.

On the other hand, when the voltage of A is high (i.e. close to Vdd), the PMOS transistor is in a high resistance state, disconnecting Vdd from Q. The NMOS transistor is in a low resistance state, connecting Vss to Q. Now, Q registers Vss.

In short, the outputs of the PMOS and NMOS transistors are complementary such that when the input is low, the output is high, and when the input is high, the output is low. No matter what the input is, the output is never left floating (charge is never stored due to wire capacitance and lack of electrical drain/ground). Because of this behavior of input and output, the CMOS circuit's output is the inverse of the input.

The transistors' resistances are never exactly equal to zero or infinity, so Q will never exactly equal Vss or Vdd, but Q will always be closer to Vss than A was to Vdd (or vice versa if A were close to Vss). Without this amplification, there would be a very low limit to the number of logic gates that could be chained together in series, and CMOS logic with billions of transistors would be impossible.

Power supply pins

See also: IC power-supply pin

The power supply pins for CMOS are called VDD and VSS, or VCC and Ground(GND) depending on the manufacturer. VDD and VSS are carryovers from conventional MOS circuits and stand for the drain and source supplies.[10] These do not apply directly to CMOS, since both supplies are really source supplies. VCC and Ground are carryovers from TTL logic and that nomenclature has been retained with the introduction of the 54C/74C line of CMOS.

Duality

An important characteristic of a CMOS circuit is the duality that exists between its PMOS transistors and NMOS transistors. A CMOS circuit is created to allow a path always to exist from the output to either the power source or ground. To accomplish this, the set of all paths to the voltage source must be the complement of the set of all paths to ground. This can be easily accomplished by defining one in terms of the NOT of the other. Due to the De Morgan's laws based logic, the PMOS transistors in parallel have corresponding NMOS transistors in series while the PMOS transistors in series have corresponding NMOS transistors in parallel.

Logic

NAND gate in CMOS logic

More complex logic functions such as those involving AND and OR gates require manipulating the paths between gates to represent the logic. When a path consists of two transistors in series, both transistors must have low resistance to the corresponding supply voltage, modelling an AND. When a path consists of two transistors in parallel, either one or both of the transistors must have low resistance to connect the supply voltage to the output, modelling an OR.

Shown on the right is a circuit diagram of a NAND gate in CMOS logic. If both of the A and B inputs are high, then both the NMOS transistors (bottom half of the diagram) will conduct, neither of the PMOS transistors (top half) will conduct, and a conductive path will be established between the output and Vss (ground), bringing the output low. If both of the A and B inputs are low, then neither of the NMOS transistors will conduct, while both of the PMOS transistors will conduct, establishing a conductive path between the output and Vdd (voltage source), bringing the output high. If either of the A or B inputs is low, one of the NMOS transistors will not conduct, one of the PMOS transistors will, and a conductive path will be established between the output and Vdd (voltage source), bringing the output high. As the only configuration of the two inputs that results in a low output is when both are high, this circuit implements a NAND (NOT AND) logic gate.

An advantage of CMOS over NMOS logic is that both low-to-high and high-to-low output transitions are fast since the (PMOS) pull-up transistors have low resistance when switched on, unlike the load resistors in NMOS logic. In addition, the output signal swings the full voltage between the low and high rails. This strong, more nearly symmetric response also makes CMOS more resistant to noise.

See Logical effort for a method of calculating delay in a CMOS circuit.

Example: NAND gate in physical layout

The physical layout of a NAND circuit. The larger regions of N-type diffusion and P-type diffusion are part of the transistors. The two smaller regions on the left are taps to prevent latchup.
Simplified process of fabrication of a CMOS inverter on p-type substrate in semiconductor microfabrication. In step 1, silicon dioxide layers are formed initially through thermal oxidation Note: Gate, source and drain contacts are not normally in the same plane in real devices, and the diagram is not to scale.

This example shows a NAND logic device drawn as a physical representation as it would be manufactured. The physical layout perspective is a "bird's eye view" of a stack of layers. The circuit is constructed on a P-type substrate. The polysilicon, diffusion, and n-well are referred to as "base layers" and are actually inserted into trenches of the P-type substrate. (See steps 1 to 6 in the process diagram below right) The contacts penetrate an insulating layer between the base layers and the first layer of metal (metal1) making a connection.

The inputs to the NAND (illustrated in green color) are in polysilicon. The transistors (devices) are formed by the intersection of the polysilicon and diffusion; N diffusion for the N device & P diffusion for the P device (illustrated in salmon and yellow coloring respectively). The output ("out") is connected together in metal (illustrated in cyan coloring). Connections between metal and polysilicon or diffusion are made through contacts (illustrated as black squares). The physical layout example matches the NAND logic circuit given in the previous example.

The N device is manufactured on a P-type substrate while the P device is manufactured in an N-type well (n-well). A P-type substrate "tap" is connected to VSS and an N-type n-well tap is connected to VDD to prevent latchup.

Cross section of two transistors in a CMOS gate, in an N-well CMOS process

Power: switching and leakage

CMOS logic dissipates less power than NMOS logic circuits because CMOS dissipates power only when switching ("dynamic power"). On a typical ASIC in a modern 90 nanometer process, switching the output might take 120 picoseconds, and happens once every ten nanoseconds. NMOS logic dissipates power whenever the transistor is on, because there is a current path from Vdd to Vss through the load resistor and the n-type network.

Static CMOS gates are very power efficient because they dissipate nearly zero power when idle. Earlier, the power consumption of CMOS devices was not the major concern while designing chips. Factors like speed and area dominated the design parameters. As the CMOS technology moved below sub-micron levels the power consumption per unit area of the chip has risen tremendously.

Broadly classifying, power dissipation in CMOS circuits occurs because of two components, static and dynamic:

Static dissipation

Both NMOS and PMOS transistors have a gate–source threshold voltage (Vth), below which the current (called sub threshold current) through the device drops exponentially. Historically, CMOS designs operated at supply voltages much larger than their threshold voltages (Vdd might have been 5 V, and Vth for both NMOS and PMOS might have been 700 mV). A special type of the transistor used in some CMOS circuits is the native transistor, with near zero threshold voltage.

SiO2 is a good insulator, but at very small thickness levels electrons can tunnel across the very thin insulation; the probability drops off exponentially with oxide thickness. Tunnelling current becomes very important for transistors below 130 nm technology with gate oxides of 20 Å or thinner.

Small reverse leakage currents are formed due to formation of reverse bias between diffusion regions and wells (for e.g., p-type diffusion vs. n-well), wells and substrate (for e.g., n-well vs. p-substrate). In modern process diode leakage is very small compared to sub threshold and tunnelling currents, so these may be neglected during power calculations.

If the ratios do not match, then there might be different currents of PMOS and NMOS; this may lead to imbalance and thus improper current causes the CMOS to heat up and dissipate power unnecessarily. Furthermore, recent studies have shown that leakage power reduces due to aging effects as a trade-off for devices to become slower. [11]

To speed up designs, manufacturers have switched to constructions that have lower voltage thresholds but because of this a modern NMOS transistor with a Vth of 200 mV has a significant subthreshold leakage current. Designs (e.g. desktop processors) which include vast numbers of circuits which are not actively switching still consume power because of this leakage current. Leakage power is a significant portion of the total power consumed by such designs. Multi-threshold CMOS (MTCMOS), now available from foundries, is one approach to managing leakage power. With MTCMOS, high Vth transistors are used when switching speed is not critical, while low Vth transistors are used in speed sensitive paths. Further technology advances that use even thinner gate dielectrics have an additional leakage component because of current tunnelling through the extremely thin gate dielectric. Using high-κ dielectrics instead of silicon dioxide that is the conventional gate dielectric allows similar device performance, but with a thicker gate insulator, thus avoiding this current. Leakage power reduction using new material and system designs is critical to sustaining scaling of CMOS.[12]

Dynamic dissipation

Charging and discharging of load capacitances

CMOS circuits dissipate power by charging the various load capacitances (mostly gate and wire capacitance, but also drain and some source capacitances) whenever they are switched. In one complete cycle of CMOS logic, current flows from VDD to the load capacitance to charge it and then flows from the charged load capacitance (CL) to ground during discharge. Therefore, in one complete charge/discharge cycle, a total of Q=CLVDD is thus transferred from VDD to ground. Multiply by the switching frequency on the load capacitances to get the current used, and multiply by the average voltage again to get the characteristic switching power dissipated by a CMOS device: .

Since most gates do not operate/switch at every clock cycle, they are often accompanied by a factor , called the activity factor. Now, the dynamic power dissipation may be re-written as .

A clock in a system has an activity factor α=1, since it rises and falls every cycle. Most data has an activity factor of 0.1.[13] If correct load capacitance is estimated on a node together with its activity factor, the dynamic power dissipation at that node can be calculated effectively.

Short-circuit power

Since there is a finite rise/fall time for both pMOS and nMOS, during transition, for example, from off to on, both the transistors will be on for a small period of time in which current will find a path directly from VDD to ground, hence creating a short-circuit current, sometimes called a crowbar current. Short-circuit power dissipation increases with the rise and fall time of the transistors.

This form of power consumption became significant in the 1990s as wires on chip became narrower and the long wires became more resistive. CMOS gates at the end of those resistive wires see slow input transitions. Careful design which avoids weakly driven long skinny wires reduces this effect, but crowbar power can be a substantial part of dynamic CMOS power.

Input protection

Parasitic transistors that are inherent in the CMOS structure may be turned on by input signals outside the normal operating range, e.g. electrostatic discharges or line reflections. The resulting latch-up may damage or destroy the CMOS device. Clamp diodes are included in CMOS circuits to deal with these signals. Manufacturers' data sheets specify the maximum permitted current that may flow through the diodes.

Analog CMOS

Further information: CMOS amplifier and Mixed-signal integrated circuit

Besides digital applications, CMOS technology is also used in analog applications. For example, there are CMOS operational amplifier ICs available in the market. Transmission gates may be used as analog multiplexers instead of signal relays. CMOS technology is also widely used for RF circuits all the way to microwave frequencies, in mixed-signal (analog+digital) applications.[citation needed]

RF CMOS

Main article: RF CMOS

RF CMOS refers to RF circuits (radio frequency circuits) which are based on mixed-signal CMOS integrated circuit technology. They are widely used in wireless telecommunication technology. RF CMOS was developed by Asad Abidi while working at UCLA in the late 1980s. This changed the way in which RF circuits were designed, leading to the replacement of discrete bipolar transistors with CMOS integrated circuits in radio transceivers.[14] It enabled sophisticated, low-cost and portable end-user terminals, and gave rise to small, low-cost, low-power and portable units for a wide range of wireless communication systems. This enabled "anytime, anywhere" communication and helped bring about the wireless revolution, leading to the rapid growth of the wireless industry.[15]

The baseband processors[16][17] and radio transceivers in all modern wireless networking devices and mobile phones are mass-produced using RF CMOS devices.[14] RF CMOS circuits are widely used to transmit and receive wireless signals, in a variety of applications, such as satellite technology (such as GPS), bluetooth, Wi-Fi, near-field communication (NFC), mobile networks (such as 3G and 4G), terrestrial broadcast, and automotive radar applications, among other uses.[18]

Examples of commercial RF CMOS chips include Intel's DECT cordless phone, and 802.11 (Wi-Fi) chips created by Atheros and other companies.[19] Commercial RF CMOS products are also used for Bluetooth and Wireless LAN (WLAN) networks.[20] RF CMOS is also used in the radio transceivers for wireless standards such as GSM, Wi-Fi, and Bluetooth, transceivers for mobile networks such as 3G, and remote units in wireless sensor networks (WSN).[21]

RF CMOS technology is crucial to modern wireless communications, including wireless networks and mobile communication devices. One of the companies that commercialized RF CMOS technology was Infineon. Its bulk CMOS RF switches sell over 1 billion units annually, reaching a cumulative 5 billion units, as of 2018.[22]

Temperature range

Conventional CMOS devices work over a range of −55 °C to +125 °C.

There were theoretical indications as early as August 2008 that silicon CMOS will work down to −233 °C (40 K).[23] Functioning temperatures near 40 K have since been achieved using overclocked AMD Phenom II processors with a combination of liquid nitrogen and liquid helium cooling.[24]

Silicon Carbide CMOS devices have been tested for a year at 500°C.[25][26]

Single-electron MOS transistors

Ultra small (L = 20 nm, W = 20 nm) MOSFETs achieve the single-electron limit when operated at cryogenic temperature over a range of −269 °C (4 K) to about −258 °C (15 K). The transistor displays Coulomb blockade due to progressive charging of electrons one by one. The number of electrons confined in the channel is driven by the gate voltage, starting from an occupation of zero electrons, and it can be set to one or many.[27]

See also

References

  1. ^ "What is CMOS Memory?". Wicked Sago. Archived from the original on 26 September 2014. Retrieved 3 March 2013.
  2. ^ Voinigescu, Sorin (2013). High-Frequency Integrated Circuits. Cambridge University Press. p. 164. ISBN 9780521873024.
  3. ^ Fairchild. Application Note 77. "CMOS, the Ideal Logic Family" Archived 2015-01-09 at the Wayback Machine. 1983.
  4. ^ "Intel® Architecture Leads the Microarchitecture Innovation Field". Intel. Archived from the original on 29 June 2011. Retrieved 2 May 2018.
  5. ^ Baker, R. Jacob (2008). CMOS: circuit design, layout, and simulation (Second ed.). Wiley-IEEE. p. xxix. ISBN 978-0-470-22941-5.
  6. ^ "1978: Double-well fast CMOS SRAM (Hitachi)" (PDF). Semiconductor History Museum of Japan. Archived from the original (PDF) on 5 July 2019. Retrieved 5 July 2019.
  7. ^ Higgins, Richard J. (1983). Electronics with digital and analog integrated circuits. Prentice-Hall. p. 101. ISBN 9780132507042. The dominant difference is power: CMOS gates can consume about 100,000 times less power than their TTL equivalents!
  8. ^ Stephens, Carlene; Dennis, Maggie (2000). "Engineering Time: Inventing the Electronic Wristwatch" (PDF). The British Journal for the History of Science. 33 (4). Cambridge University Press: 477–497 (485). doi:10.1017/S0007087400004167. ISSN 0007-0874.
  9. ^ "What is CMOS?". IONOS Digitalguide. Retrieved 2022-01-21.
  10. ^ "Archived copy" (PDF). Archived from the original (PDF) on 2011-12-09. Retrieved 2011-11-25.{{cite web}}: CS1 maint: archived copy as title (link)
  11. ^ Martínez, A.L.H.; Khursheed, S.; Rossi, D. (2020). "Leveraging CMOS Aging for Efficient Microelectronics Design". 2020 IEEE 26th International Symposium on On-Line Testing and Robust System Design (IOLTS). pp. 1–4. doi:10.1109/IOLTS50870.2020.9159742. ISBN 978-1-7281-8187-5. S2CID 225582202.
  12. ^ A good overview of leakage and reduction methods are explained in the book Leakage in Nanometer CMOS Technologies Archived 2011-12-02 at the Wayback Machine ISBN 0-387-25737-3.
  13. ^ Moiseev, Konstantin; Kolodny, Avinoam; Wimer, Shmuel (September 2008). "Timing-aware power-optimal ordering of signals". ACM Trans. Des. Autom. Electron. Syst. 13 (4). Article 65. CiteSeerX 10.1.1.222.9211. doi:10.1145/1391962.1391973. S2CID 18895687.
  14. ^ a b O'Neill, A. (2008). "Asad Abidi Recognized for Work in RF-CMOS". IEEE Solid-State Circuits Society Newsletter. 13 (1): 57–58. doi:10.1109/N-SSC.2008.4785694. ISSN 1098-4232.
  15. ^ Daneshrad, Babal; Eltawil, Ahmed M. (2002). "Integrated Circuit Technologies for Wireless Communications". Wireless Multimedia Network Technologies. The International Series in Engineering and Computer Science. 524. Springer US: 227–244. doi:10.1007/0-306-47330-5_13. ISBN 0-7923-8633-7.
  16. ^ Chen, Wai-Kai (2018). The VLSI Handbook. CRC Press. pp. 60–2. ISBN 9781420005967.
  17. ^ Morgado, Alonso; Río, Rocío del; Rosa, José M. de la (2011). Nanometer CMOS Sigma-Delta Modulators for Software Defined Radio. Springer. p. 1. ISBN 9781461400370.
  18. ^ Veendrick, Harry J. M. (2017). Nanometer CMOS ICs: From Basics to ASICs. Springer. p. 243. ISBN 9783319475974.
  19. ^ Nathawad, L.; Zargari, M.; Samavati, H.; Mehta, S.; Kheirkhaki, A.; Chen, P.; Gong, K.; Vakili-Amini, B.; Hwang, J.; Chen, M.; Terrovitis, M.; Kaczynski, B.; Limotyrakis, S.; Mack, M.; Gan, H.; Lee, M.; Abdollahi-Alibeik, B.; Baytekin, B.; Onodera, K.; Mendis, S.; Chang, A.; Jen, S.; Su, D.; Wooley, B. "20.2: A Dual-band CMOS MIMO Radio SoC for IEEE 802.11n Wireless LAN" (PDF). IEEE Entity Web Hosting. IEEE. Retrieved 22 October 2016.
  20. ^ Olstein, Katherine (Spring 2008). "Abidi Receives IEEE Pederson Award at ISSCC 2008". SSCC: IEEE Solid-State Circuits Society News. 13 (2): 12. doi:10.1109/N-SSC.2008.4785734. S2CID 30558989.
  21. ^ Oliveira, Joao; Goes, João (2012). Parametric Analog Signal Amplification Applied to Nanoscale CMOS Technologies. Springer. p. 7. ISBN 9781461416708.
  22. ^ "Infineon Hits Bulk-CMOS RF Switch Milestone". EE Times. 20 November 2018. Retrieved 26 October 2019.
  23. ^ Edwards C., "Temperature control", Engineering & Technology 26 July – 8 August 2008, IET.
  24. ^ Moorhead, Patrick (January 15, 2009). "Breaking Records with Dragons and Helium in the Las Vegas Desert". blogs.amd.com/patmoorhead. Archived from the original on September 15, 2010. Retrieved 2009-09-18.
  25. ^ Clark, D.T.; Ramsay, E.P.; Murphy, A.E.; Smith, D.A.; Thompson, Robin.F.; Young, R.A.R.; Cormack, J.D.; Zhu, C.; Finney, S.; Fletcher, J. (2011). "High Temperature Silicon Carbide CMOS Integrated Circuits". Materials Science Forum. 679–680: 726–729. doi:10.4028/www.scientific.net/msf.679-680.726. S2CID 110071501.
  26. ^ Mantooth, Alan; Zetterling, Carl-Mikael; Rusu, Ana (28 April 2021). "The Radio We Could Send to Hell: Silicon carbide radio circuits can take the volcanic heat of Venus". IEEE Spectrum.
  27. ^ Prati, E.; De Michielis, M.; Belli, M.; Cocco, S.; Fanciulli, M.; Kotekar-Patil, D.; Ruoff, M.; Kern, D. P.; Wharam, D. A.; Verduijn, J.; Tettamanzi, G. C.; Rogge, S.; Roche, B.; Wacquez, R.; Jehl, X.; Vinet, M.; Sanquer, M. (2012). "Few electron limit of n-type metal oxide semiconductor single electron transistors". Nanotechnology. 23 (21): 215204. arXiv:1203.4811. Bibcode:2012Nanot..23u5204P. doi:10.1088/0957-4484/23/21/215204. PMID 22552118. S2CID 206063658.

Further reading

See also: List of books about 4000-series integrated circuits
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