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Repeater insertion is a technique used to reduce time delays associated with long wire lines in integrated circuits. This technique involves cutting the long wire into one or more shorter wires, and then inserting a repeater between each pair of newly created short wires.[1]
The time it takes for a signal to travel from one end of a wire to the other end is known as wire-line delay or just delay. In an integrated circuit, this delay is characterized by RC, the resistance of the wire (R) multiplied by the wire's capacitance (C). Thus, if the wire's resistance is 100 ohms and its capacitance is 0.01 microfarad (μF), the wire's delay is one microsecond (μs).[2]
The resistance of a wire on an integrated circuit is directly proportional, or linear, according to the wire's length. If a 1 mm length of the wire has 100 ohms resistance, then a 2 mm length will have 200 ohms resistance.[3]
For the purposes of our highly simplified discussion, the capacitance of a wire also increases linearly along its length. If a 1 mm length of the wire has 0.01 μF capacitance, a 2 mm length of the wire will have 0.02 μF, a 3 mm wire will have 0.03 μF, and so on.
Thus, the time delay through a wire increases with the square of the wire's length. This is true, to first order, for any wire whose cross-section remains constant along the length of the wire.
| Wire length | Resistance | Capacitance | Time delay |
|---|---|---|---|
| 1 mm | 100 ohm | 0.01 μF | 1 μs |
| 2 mm | 200 ohm | 0.02 μF | 4 μs |
| 3 mm | 300 ohm | 0.03 μF | 9 μs |
A consequence of this behavior is that, while a single 2 mm length of wire has a delay of 4 μs. Two separate 1 mm wires only have a delay of 1 μs each and cover the same distance in half the time. By cutting the wire in half, one can double its speed.[4]
To make this science trick work properly, an active circuit must be placed between the two separate wires so as to move the signal from one to the next. An active circuit used for such a purpose is known as a repeater. In a CMOS integrated circuit, the repeater is often a simple inverter.
Reducing the delay of a wire by cutting it in half and inserting a repeater is known as repeater insertion. The cost of this procedure is the additional new delay through the repeater itself, plus power cost because the repeater is an active circuit that must be powered, whereas the plain unrepeated wire was originally an unpowered passive component.[5]
For more details, see for example Anikreddy and Burleson's paper, Repeater Insertion in deep sub-micron CMOS: Ramp-based Analytical Model and Placement Sensitivity Analysis, in ISCAS 2000, the IEEE International Symposium on Circuits and Systems, May 28–31, 2000, Geneva, Switzerland (https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=856173).
References
edit- ^ Deutsch, A.; Kopcsay, G.V.; Restle, P.J.; Smith, H.H.; Katopis, G.; Becker, W.D.; Coteus, P.W.; Surovic, C.W.; Rubin, B.J.; Dunne, R.P.; Gallo, T.; Jenkins, K.A.; Terman, L.M.; Dennard, R.H.; Sai-Halasz, G.A. (1997). "When are transmission-line effects important for on-chip interconnections?". IEEE Transactions on Microwave Theory and Techniques. 45 (10): 1836–1846. doi:10.1109/22.641781. ISSN 0018-9480.
- ^ Dhiman, Rohit; Chandel, Rajeevan (2016-09-09). "Delay analysis of buffer inserted sub-threshold interconnects". Analog Integrated Circuits and Signal Processing. 90 (2): 435–445. doi:10.1007/s10470-016-0860-8. ISSN 0925-1030.
- ^ "3 Interfacing between Digital Logic Circuits", Digital Integrated Circuits, CRC Press, pp. 501–528, 2003-12-15, doi:10.1201/b12491-15, ISBN 978-0-203-48690-0, retrieved 2024-09-16
- ^ MOORE, PHILLIP W.; VENAYAGAMOORTHY, GANESH K. (June 2006). "Evolving Digital Circuits Using Hybrid Particle Swarm Optimization and Differential Evolution". International Journal of Neural Systems. 16 (3): 163–177. doi:10.1142/s0129065706000585. ISSN 0129-0657.
- ^ El-Moursy, Magdy A.; Friedman, Eby G. (July 2007). "Wire shaping of RLC interconnects". Integration. 40 (4): 461–472. doi:10.1016/j.vlsi.2006.06.002. ISSN 0167-9260.