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- ArticleApril 2001
A design framework to efficiently explore energy-delay tradeoffs
CODES '01: Proceedings of the ninth international symposium on Hardware/software codesignPages 260–265https://doi.org/10.1145/371636.371752Comprehensive exploration of the design space parameters at the system-level is a crucial task to evaluate architectural tradeoffs accounting for both energy and performance constraints. In this paper, we propose a system-level design methodology for ...
- ArticleApril 2001
Processor frequency setting for energy minimization of streaming multimedia application
CODES '01: Proceedings of the ninth international symposium on Hardware/software codesignPages 249–253https://doi.org/10.1145/371636.371747In this paper, we describe a software-controlled approach for adaptively minimizing energy in embedded systems for realtime multimedia processing. Energy is optimized by clock speed setting: the software controller dynamically adjusts processor clock ...
- ArticleApril 2001
Hybrid global/local search strategies for dynamic voltage scaling in embedded multiprocessors
CODES '01: Proceedings of the ninth international symposium on Hardware/software codesignPages 243–248https://doi.org/10.1145/371636.371744In this paper, we explore a hybrid global/local search optimization framework for dynamic voltage scaling in embedded multiprocessor systems. The problem is to find, for a multiprocessor system in which the processors are capable of dynamically varying ...
- ArticleApril 2001
Dynamic I/O power management for hard real-time systems
CODES '01: Proceedings of the ninth international symposium on Hardware/software codesignPages 237–242https://doi.org/10.1145/371636.371742Power consumption is an important design parameter for embedded and portable systems. Software-controlled (or dynamic) power management (DPM) has recently emerged as an attractive alternative to inflexible hardware solutions. DPM for hard real-time ...
- ArticleApril 2001
Empirical comparison of software-based error detection and correction techniques for embedded systems
CODES '01: Proceedings of the ninth international symposium on Hardware/software codesignPages 230–235https://doi.org/10.1145/371636.371739“Function Tokens” and “NOP Fills” are two methods proposed by various authors to deal with Instruction Pointer corruption in microcontrollers, especially in the presence of high electromagnetic interference levels. An empirical analysis to assess and ...
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- ArticleApril 2001
Logic optimization and code generation for embedded control applications
CODES '01: Proceedings of the ninth international symposium on Hardware/software codesignPages 225–229https://doi.org/10.1145/371636.371735We address software optimization for embedded control systems. The Esterel language is used as the front-end specification; Esterel compiler v6 is used to partition the control circuit and data path; the resulting intermediate representation of the ...
- ArticleApril 2001
Whole program compilation for embedded software: the ADSL experiment
CODES '01: Proceedings of the ninth international symposium on Hardware/software codesignPages 214–218https://doi.org/10.1145/371636.371732The increasing complexity and decreasing time-to-market of embedded software forces designers to write more modular and reusable code, using for example object-oriented techniques and languages such as C++. The resulting memory and runtime overhead ...
- ArticleApril 2001
Formal synthesis and code generation of embedded real-time software
CODES '01: Proceedings of the ninth international symposium on Hardware/software codesignPages 208–213https://doi.org/10.1145/371636.371729Due to rapidly increasing system complexity, shortening time-to-market, and growing demand for hard real-time systems, formal methods are becoming indispensable in the synthesis of embedded systems, which must satisfy stringent temporal, memory, and ...
- ArticleApril 2001
A generic wrapper architecture for multi-processor SoC cosimulation and design
CODES '01: Proceedings of the ninth international symposium on Hardware/software codesignPages 195–200https://doi.org/10.1145/371636.371722In communication refinement with multiple communication protocols and abstraction levels, the system specification is described by heterogeneous components in terms of communication protocols and abstraction levels. To adapt each heterogeneous component ...
- ArticleApril 2001
Minimizing system modification in an incremental design approach
CODES '01: Proceedings of the ninth international symposium on Hardware/software codesignPages 183–188https://doi.org/10.1145/371636.371718In this paper we present an approach to mapping and scheduling of distributed embedded systems for hard real-time applications, aiming at minimizing system modification cost. We consider an incremental design process that starts from an already existing ...
- ArticleApril 2001
Parameterised system design based on genetic algorithms
CODES '01: Proceedings of the ninth international symposium on Hardware/software codesignPages 177–182https://doi.org/10.1145/371636.371714A recent reduction in the time to market has led to the development of a new approach to IP-based design in which a highly parametric pre-designed system-on-a-chip is configured according to the application it will have to execute. The greatest problems ...
- ArticleApril 2001
Task concurrency management methodology to schedule the MPEG4 IM1 player on a highly parallel processor platform
CODES '01: Proceedings of the ninth international symposium on Hardware/software codesignPages 170–177https://doi.org/10.1145/371636.371712This paper addresses the concurrent task management of complex multi-media systems, like the MPEG4 IM1 player, with emphasis on how to derive energy-cost vs time-budget curves through task scheduling on a multi-processor platform. Starting from the ...
- ArticleApril 2001
Scheduling-based code size reduction in processors with indirect addressing mode
CODES '01: Proceedings of the ninth international symposium on Hardware/software codesignPages 165–169https://doi.org/10.1145/371636.371710DSPs are typically equipped with indirect addressing modes with auto-increment and auto-decrement, which provide efficient address arithmetic calculations. Such an addressing mode is maximally utilized by careful placement of variables in storage, ...
- ArticleApril 2001
Optimal acyclic fine-grain scheduling with cache effects for embedded and real time systems
CODES '01: Proceedings of the ninth international symposium on Hardware/software codesignPages 159–164https://doi.org/10.1145/371636.371709To sustain the increases in processor performance, embedded and real-time systems need to find the best total schedule time when compiling their application. The optimal acyclic scheduling problem is a classical challenge which has been formulated using ...
- ArticleApril 2001
A constraint-based application model and scheduling techniques for power-aware systems
CODES '01: Proceedings of the ninth international symposium on Hardware/software codesignPages 153–158https://doi.org/10.1145/371636.371707New embedded systems must be power-aware, not just low-power. That is, they must track their power sources and the changing power and performance constraints imposed by the environment. Moreover, they must fully explore and integrate many novel power ...
- ArticleApril 2001
A constructive algorithm for memory-aware task assignment and scheduling
CODES '01: Proceedings of the ninth international symposium on Hardware/software codesignPages 147–152https://doi.org/10.1145/371636.371706This paper presents a constructive algorithm for memory-aware task assignment and scheduling, which is a part of the prototype system MATAS. The algorithm is well suited for image and video processing applications which have hard memory constraints as ...
- ArticleApril 2001
A systematic approach to software peripherals for embedded systems
CODES '01: Proceedings of the ninth international symposium on Hardware/software codesignPages 140–145https://doi.org/10.1145/371636.371704The continued growth of microprocessors' performance and the need for better CPU utilization, has led to the introduction of the software peripherals' approach: By this term we refer to software modules that can successfully emulate peripherals that, ...
- ArticleApril 2001
A trace transformation technique for communication refinement
CODES '01: Proceedings of the ninth international symposium on Hardware/software codesignPages 134–139https://doi.org/10.1145/371636.371703Models of computation like Kahn and dataflow process networks provide convenient means for modeling signal processing applications. This is partly due to the abstract primitives that these models offer for communication between concurrent processes. ...
- ArticleApril 2001
Deriving hard real-time embedded systems implementations directly from SDL specifications
CODES '01: Proceedings of the ninth international symposium on Hardware/software codesignPages 128–133https://doi.org/10.1145/371636.371702Object-Oriented methodologies together with Formal Description Techniques (FDT) are a promising way to deal with the increasing complexity of hard real-time embedded systems. However, FDTs do not take into account non-functional aspects as real-time ...
- ArticleApril 2001
Area-efficient buffer binding based on a novel two-port FIFO structure
CODES '01: Proceedings of the ninth international symposium on Hardware/software codesignPages 122–127https://doi.org/10.1145/371636.371700In this paper, we address the problem of minimizing buffer storage requirement in buffer binding for SDF (Synchronous Dataflow) graphs. First, we propose a new two-port FIFO buffer structure that can be efficiently shared by two producer/consumer pairs. ...