Within the design arena of modern devices based on cutting-edge processor cores, the availability of effective verification, validation and test methodologies able to work on high-level descriptions of processor cores represents an interesting advantage,...

Because of the aggressive scaling of integrated circuits and the given limits of atomic scales, circuit designers have to become more and more aware of the arising reliability and yield concerns. So far, only very little research efforts have been put ...

Statistical process variations are a critical issue to define circuit design strategies to ensure high yield in sub-100nm technologies. This work focuses on hold time violation probabilities in sub-100 nm technologies. The variability in flip-flop race ...

This paper presents the design and measurement results of a novel VCDL (Voltage Controlled Delay Line). Based on the multiphase ring oscillator technique, it offers two outputs in phase quadrature. These last ones allow the Factorial DLL (F-DLL) to be ...

The multiplication of a variable by multiple constants, i.e., the multiple constant multiplications (MCM), has been a central operation and performance bottleneck in many applications, such as finite impulse response (FIR) filters and linear transforms. ...

This work presents a high throughput and low cost architecture for the Context Adaptive Variable Length Decoder (CAVLD) of the H.264/AVC video coding standard. Usually, a large number of memory bits and memory accesses are required to decode the CAVLD ...

The purpose of this work is the proposal of a 10-Bit / 1 MSPS Analog to Digital Converter (ADC) with error correction to match the requirements of a CMOS wavefront sensor for ophthalmic applications. The developed ADC is a combination of different ...

The majority of networks subject to routing in almost every FPGA design consist of networks with only 2 to 4 terminals. These usually connect to directly adjacent logic cells. In order to make best use of this circumstance commercial FPGA architecture ...

Due to the vast number of alternatives in the design space of NoC-based MPSoCs, fast and accurate performance evaluation approaches can result in earlier - and often better - design decisions. Important design metrics for mobile embedded systems include ...

This work presents the design and characterization of a CMOS voltage-to-current (V-I) converter with a current range from -100 μA to 100 μA. The V-I converter has a power consumption of approximately 0.6 mW and its final area was 0.022 mm² in 0.35 μm ...

As the complexity of designs increase and technologies scale down, devices are subject to new types of malfunctions and failures. Network-on-chip routers are responsible to ensure the proper communication of on-chip cores, and the buffers present in the ...

The use of quaternary logic has been presented as a cost-effective solution to tackle the increasing area and power consumption of million-gate systems. This paper discusses the problem of testing a configurable logic block based on quaternary logic ...

An LC-VCO design optimization, based on the g_m/I_D methodology, is presented throughout this work, highlighting how, by applying all regions of inversion of the MOS transistor, the trade-off between phase noise and current consumption can be optimized ...

This paper describes the design of a low power MPEG-1 motion vector reconstructor using behavioural synthesis methodology. Various techniques, such as appropriate voltage scaling after clock and operations throughput selection, and reduction of ...

This paper presents a compact charge-pump gate driver (CPGD) that dynamically adjusts the driving gate-source voltage V_{GS_SW} of on-chip power switches, following stringent load transients in amplitude and duration. Owing to its simple topology, the CPGD ...

This paper covers an overview of multichannel massively parallel biosensing device dedicated for neural recording from the cortex. Attention is paid to describe the design techniques and assembly methods of high reliability Microsystems. These devices ...

With the growth of number of transistors, thermal density and market drive towards battery power, the necessity to develop low power integrated circuits is evident. There are several methodologies and techniques that help in the development of this type ...

A high linearity CMOS RF (radio frequency) power amplifier, which has the advantage of being low-cost and easily integrated on chip has become the technology of choice for RFID readers. This work demonstrates a 3.3V single voltage self-biased 2.4GHz--...

This paper describes the design, and experimental characterization of cross inductors in a 0.35μm CMOS technology. The Sonnet tools were used to simulate and evaluate the performance of the new inductor structure, whose core has perpendicular crossed ...

Homodyne receivers are widely used in modern communication systems, as they can be integrated in a single integrated circuit. Despite their remarkable advantages, they are very sensitive to even order distortion. In this paper we present a circuit which ...