Voltage controlled delay line with phase quadrature outputs for [0.9-4] GHz F-DLL dedicated to zero-IF multi-standard LO
Article No.: 44, Pages 1 - 6
Abstract
This paper presents the design and measurement results of a novel VCDL (Voltage Controlled Delay Line). Based on the multiphase ring oscillator technique, it offers two outputs in phase quadrature. These last ones allow the Factorial DLL (F-DLL) to be zero-IF compliant and so a good candidate for multi-standard LO. The proposed circuit has been fabricated using 130 nm CMOS SOI technology from STMicroelectronics. Measurements confirm the low quadrature phase error of the topology and its ability to synthesize the [0.9-4] GHz band, being suited for GSM up to WIMAX applications.
References
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Index Terms
- Voltage controlled delay line with phase quadrature outputs for [0.9-4] GHz F-DLL dedicated to zero-IF multi-standard LO
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Published In
August 2009
325 pages
ISBN:9781605587059
DOI:10.1145/1601896
- General Chair:
- Ivan Saraiva,
- Program Chairs:
- Renato Perez Ribas,
- Calvin Plett
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- SBC: Brazilian Computer Society
- SIGDA: ACM Special Interest Group on Design Automation
- SBMICRO: Brazilian Microelectronics Society
- IEEE Circuits & Systems Society
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Association for Computing Machinery
New York, NY, United States
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Published: 31 August 2009
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SBCCI '09
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- SBC
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SBCCI '09: 22nd Symposium on Integrated Circuits and System Design
August 31 - September 3, 2009
Natal, Brazil
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SBCCI '09 Paper Acceptance Rate 50 of 119 submissions, 42%;
Overall Acceptance Rate 133 of 347 submissions, 38%
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