In this paper, we propose an extended layered decoding approach for low density parity check (LDPC) codes. Compared to conventional layered decoding algorithms, the proposed approach has no constraint in the column weight of each layer. Hence, it ...

Redundancy in the output code, as instrument to reduce the impact of non-idealities in different architectures of two-step A to D converters, is investigated. A circuit model capable of providing an estimate of the required sizes for passive components ...

In this paper, an I/Q channel 12bits 40MS/s Pipeline Analog to Digital Converter that is able to apply to WLAN/WMAN system is proposed. The proposed ADC integrates DLL based duty-correction circuit which corrects the fluctuations in the duty cycle ...

Clock distribution networks are extremely critical from a performance and power standpoint. They account for about 20-30% of the total power dissipated in current generation microprocessors. Many three-dimensional (3D) schemes propose to reduce ...

The main contribution of this work is an analytical model for finding the upper bound on the temperature difference among various locations on the die. The proposed model can be used in many applications, such as estimation of maximum temperature ...

This paper proposes a new method to estimate static power dissipation in digital circuits by evaluating simultaneously subthreshold and gate oxide leakage currents. The estimation method is performed over logic cells, including CMOS complex gates with ...

This paper proposes a hybrid memory architecture which consists of the following two regions; 1) a dynamic power conscious region which uses low Vdd and Vth and 2) a static power conscious region which uses high Vdd and Vth. This paper also proposes an ...

Due to the frequent access, the instruction cache is usually a major power consumer. Based on the frequent opcode locality, where a small number of opcodes often account for a large portion of instruction executions, we propose a power-efficient ...

Sub-threshold leakage in SRAM based cache memories is becoming a predominant source of power consumption in deep-sub micron CMOS designs. Phase Change Random Access Memory (PRAM), a high density, fast access, non-volatile memory is being considered as a ...

In this paper, we propose statistical sampling techniques in estimating the mean and distribution of full-chip leakage current under process variations. The stratified random sampling procedures are used to estimate the mean and variance of the full-chip ...

Body-biasing is expected to be a common design technique, then area efficient implementation in layout has been demanded. Body-biasing outside standard cells is one of possible layouts. However in this case body-bias controllability, especially when ...

Share of leakage in cache memories is increasing with technology scaling. Studies show that most stored bits in instruction caches are zero, and hence, asymmetric SRAM cells which dissipate less leakage when storing 0, effectively reduce leakage with ...

Phase-based tuning methodologies specialize system parameters for each application phase of execution. Parameters are varied during execution, as opposed to remaining fixed as in an application-based tuning methodology. Prior work and logic suggests ...

This paper presents in-order pulsed charge recycling to reduce energy consumption in an off-chip data bus. The proposed technique performs charge recycling by employing three different steps. At the beginning of an off-chip data bus transaction, i) ...

We present electrical models for a carbon nanotube capacitor with high capacitance per unit area. We begin by introducing the concept of using vertically grown carbon nanotubes to develop a carbon nanotube capacitor. Three potential structures of the ...

Testing the genuineness of a manufactured chip is an important step in an IC product life cycle. This becomes more prominent with the outsourcing of the manufacturing process, since the manufacturer may tamper the internal circuit behavior using Trojan ...

As VLSI design complexity is continuously increasing, the yield loss due to via failure becomes more significant. Adding a redundant via adjacent to each single via is a well-known and highly recommended method to reduce yield loss due to via failure. ...

This paper addresses the problem of increasing unknowns in the output response data by exploring reiterative LFSR reseeding based X-masking. This approach takes advantage of the data correlation in the output response data to enable LFSR encoded masks ...

The stochastic sensor network-on-chip (SSNOC) was recently proposed as an effective computational paradigm for jointly achieving energy-efficiency and robustness in nanoscale processes. In this paper, we study the trends in energy-efficiency and ...

In various signal processing applications, decomposition and analysis of non-stationary signals is a challenging problem. In this work, we present a computationally efficient method, fast chirplet signal decomposition (FCSD) algorithm, for decomposing ...