Arithmetic and datapath circuits

19 Results for: Book/Issue: MICRO 31: Proceedings of the 31st annual ACM/IEEE international symposium on MicroarchitectureEdit SearchSave SearchRSS

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Unified assign and schedule: a new approach to scheduling for clustered register file microarchitectures

Predicting indirect branches via data compression

Widening resources: a cost-effective technique for aggressive ILP architectures

A novel renaming scheme to exploit value temporal locality through physical register reuse and unification

Understanding the differences between value prediction and instruction reuse

Code compression based on operand factorization

Putting the fill unit to work: dynamic optimizations for trace cache microprocessors

Load latency tolerance in dynamically scheduled processors

Predictive techniques for aggressive load speculation

Better global scheduling using path profiles

Effective cluster assignment for modulo scheduling

Split-path enhanced pipeline scheduling for loops with control flows

Task selection for a multiscalar processor

The YAGS branch prediction scheme

Dataflow analysis of branch mispredictions and its application to early resolution of branch outcomes

Analyzing the working set characteristics of branch execution

Evaluating MMX technology using DSP and multimedia applications

Simple vector microprocessors for multimedia applications

MICRO 31: Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture