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- ArticleApril 2005
A Multiple Associative Model to Support Branches in Data Parallel Applications using the Manager-Worker Paradigm
IPDPS '05: Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 14 - Volume 15Page 266.2https://doi.org/10.1109/IPDPS.2005.48ASC (Associative Computing Model) and MASC (Multiple Associative Computing Model) have long been studied in the Department of Computer Science at Kent State University While the previous studies provide the background and the basic definition of the ...
- ArticleApril 2005
TiNy Threads: A Thread Virtual Machine for the Cyclops64 Cellular Architecture
IPDPS '05: Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 14 - Volume 15Page 265.2https://doi.org/10.1109/IPDPS.2005.434This paper presents the design and implementation of a thread virtual machine, called TNT (or TiNy-Threads) for the IBM Cyclops64 architecture (the latest Cyclops architecture that employs a unique multiprocessor-on-a-chip design with a very large ...
- ArticleApril 2005
Stream PRAM
IPDPS '05: Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 14 - Volume 15Page 265.1https://doi.org/10.1109/IPDPS.2005.412Parallel random access memory, or PRAM, is a now venerable model of parallel computation that that still retains its usefulness for the design and analysis of parallel algorithms. Parallel computational models proposed after PRAM address short comings ...
- ArticleApril 2005
Memory In Processor-Supercomputer On a Chip: Processor Design and Execution Semantics for Massive Single-Chip Performance
IPDPS '05: Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 14 - Volume 15Page 263.2https://doi.org/10.1109/IPDPS.2005.279The MIP S.C.O.C was designed to overcome the Von-Neumann bottleneck and develop massive on-chip parallelism to achieve Teraflop scale single chip performance. We case study here a specific 2 MB MIP node that has a 128 bit datapath. This paper also ...
- ArticleApril 2005
FPGA Implementations of the Massively Parallel GCA Model
IPDPS '05: Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 14 - Volume 15Page 262.2https://doi.org/10.1109/IPDPS.2005.229The GCA (Global Cellular Automata) model is a very interesting and flexible model which can be used to implement all kind of parallel algorithms. The GCA model consists of a field of cells similar the Cellular Automata model. Each cell has links to a ...
- ArticleApril 2005
Extracting Speedup From C-Code With Poor Instruction-Level Parallelism
IPDPS '05: Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 14 - Volume 15Page 264.2https://doi.org/10.1109/IPDPS.2005.216Scientific computing and multimedia applications frequently call loop-intensive functions that dominate execution time. Applying homogeneous, parallel processors (e.g. single-instruction, multiple-data (SIMD) and very-long instruction word (VLIW)) is a ...
