Article

TiNy Threads: A Thread Virtual Machine for the Cyclops64 Cellular Architecture

Authors:

Juan del Cuvillo,

Guang R. GaoAuthors Info & Claims

IPDPS '05: Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 14 - Volume 15

Page 265.2

https://doi.org/10.1109/IPDPS.2005.434

Published: 04 April 2005 Publication History

Abstract

This paper presents the design and implementation of a thread virtual machine, called TNT (or TiNy-Threads) for the IBM Cyclops64 architecture (the latest Cyclops architecture that employs a unique multiprocessor-on-a-chip design with a very large number of hardware thread units and embedded memory) - as the cornerstone of the C64 system software. We highlight how to achieve high efficiency by mapping (and matching) the TNT thread model directly to the Cyclops ISA features assisted by a native TNT thread runtime library. Major results of our experimental study demonstrate good efficiency, scalability and usability of our TNT model/implementation.

References

[1]

G. Almási, C. Cascaval, J. G. Castaños, M. Denneau, D. Lieber, J. E. Moreira, and H. S. Warren, Jr. Dissecting Cyclops: A detailed analysis of a multithreaded architecture. ACM SIGARCH Computer Architecture News, 31(1):26-38, March 2003.

[2]

G. S. Almási, C. Cascaval, J. G. Castaños, M. Denneau, W. Donath, M. Eleftheriou, M. Giampapa, H. Ho, D. Lieber, J. E. Moreira, D. Newns, M. Snir, and H. S. Warren, Jr. Demonstrating the scalability of a molecular dynamics application on a petaflops computer. International Journal of Parallel Programming, 30(4):317-351, August 2002.

[3]

S. Biallas. PearPC - PowerPC architecture emulator, May 2004.

[4]

D. C. Burger and T. M. Austin. The SimpleScalar tool set, version 2.0. Technical Report 1342, Computer Sciences Department, University of Wisconsin at Madison, Madison, Wisconson, June 1997.

[5]

C. Cascaval, J. G. Castaños, L. Ceze, M. Denneau, M. Gupta, D. Lieber, J. E. Moreira, K. Strauss, and H. S. Warren, Jr. Evaluation of a multithreaded architecture for cellular computing. In Proceedings of the Eighth International Symposium on High-Performance Computer Architecture, pages 311-321, Boston, Massachusetts, February 02-06, 2002.

[6]

D. E. Culler, S. C. Goldstein, K. E. Schauser, and T. von Eicken. TAM - a compiler controlled threaded abstract machine. Journal of Parallel and Distributed Computing, 18:347-370, July 1993.

[7]

J. B. del Cuvillo, Z. Hu, W. Zhu, F. Chen, and G. R. Gao. Toward a software infrastrucutre for the Cyclops64 cellular architecture. CAPSL Technical Memo 55, Department of Electrical and Computer Engineering, University of Delaware, Newark, Delaware, April 2004.

[8]

J. B. del Cuvillo, R. Klosiewicz, and Y. Zhang. A software development kit for DIMES. CAPSL Technical Note 10, Department of Electrical and Computer Engineering, University of Delaware, Newark, Delaware, September 2003.

[9]

U. Drepper and I. Molnar. The native POSIX thread library for linux. Technical report, Read Hat, Inc., January 2003.

[10]

M. Frigo, C. E. Leiserson, and K. H. Randall. The implementation of the Cilk-5 multithreaded language. In Proceedings of the ACM SIGPLAN '98 Conference on Programming Language Design and Implementation, pages 212-223, Montréal, Québec, June 17-19, 1998.

[11]

M. Haines and K. Langedoen. Platform-independent runtime optimizations using OpenThreads. In Proceedings of the 11th International Parallel Processing Symposium, pages 460-466, Geneva, Switzerland, April 1-5, 1997.

[12]

L. Kalè, J. Yelon, and T. Knauff. Threads for interoperable parallel programming. In Proceedings of the 9th International Workshop on Languages and Compilers for Parallel Computing, number 1239 in Lecture Notes in Computer Science, pages 534-552, Ithaca, New York, August 8-10, 1996.

[13]

D. Keppel. Tools and techniques for building fast portable threads packages. Technical Report UW-CSE-93-05-06, Department of Computer Science and Engineering, University of Washington, May 1993.

[14]

F. Mueller. Pthreads library interface. Technical report, Department of Computer Science, Florida State University, July 1993.

[15]

D. S. Nikolopoulos, E. D. Polychronopoulos, and T. S. Papatheodorou. Efficient runtime thread management for the Nano-Threads programming model. In Proceedings of the 2nd IPPS/SPDP Workshop on Runtime Systems for Parallel Programming, pages 183-194, Orlando, Florida, March 30, 1998.

[16]

D. G. Perez, G. Mouchard, and O. Temam. Microlib: A case for the quantitative comparison of micro-architecture mechanisms. In Proceedings of the 37th Annual International Symposium on Microarchitecture, pages 43-54, Portland, Oregon, December 4-8, 2004.

[17]

J. Rosenberg. LWP user manual. Technical Report CMUITC- 85-037, Information Technology Center, Carnegie-Mellon University, June 1985.

[18]

H. Sakane, L. Yakay, V. Karna, C. Leung, and G. R. Gao. DIMES: An iterative emulation platform for multiprocessor-system-on-chip designs. In Proceedings of the IEEE International Conference on Field-Programmble Technology, Tokio, Japan, December 15-17, 2003.

[19]

K. B. Theobald. EARTH: An Efficient Architecture for Running Threads. PhD thesis, McGill University, Montréal, Québec, May 1999.

[20]

M. Vachharajani, N. Vachharajani, D. A. Penry, J. A. Blome, and D. I. August. Microarchitectural exploration with liberty. In Proceedings of the 35th Annual International Symposium on Microarchitecture, pages 271-282, Istanbul, Turkey, November 18-22, 2002.

[21]

B. Weissman. Active threads: An extensible and portable light-weight thread system. Technical Report ICSI TR-97- 036, International Computer ScienceInstitute, University of California at Berkeley, October 1997.

Cited By

Ghosh SCuevas MCampanoni SDinda PCuicchi CQualters IKramer W(2020)Compiler-based timing for extremely fine-grain preemptive parallelismProceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis10.5555/3433701.3433771(1-15)Online publication date: 9-Nov-2020
https://dl.acm.org/doi/10.5555/3433701.3433771
Jang CLee JSeo SLee JEidt CHoller ASrinivasan UAmarasinghe S(2012)An automatic code overlaying technique for multicores with explicitly-managed memory hierarchiesProceedings of the Tenth International Symposium on Code Generation and Optimization10.1145/2259016.2259045(219-229)Online publication date: 31-Mar-2012
https://dl.acm.org/doi/10.1145/2259016.2259045
St. John TDennis JGao GGuo MHuang Z(2012)Massively parallel breadth first search using a tree-structured memory modelProceedings of the 2012 International Workshop on Programming Models and Applications for Multicores and Manycores10.1145/2141702.2141715(115-123)Online publication date: 26-Feb-2012
https://dl.acm.org/doi/10.1145/2141702.2141715
Show More Cited By

Index Terms

TiNy Threads: A Thread Virtual Machine for the Cyclops64 Cellular Architecture

Recommendations

Inter-core prefetching for multicore processors using migrating helper threads
ASPLOS XVI: Proceedings of the sixteenth international conference on Architectural support for programming languages and operating systems

Multicore processors have become ubiquitous in today's systems, but exploiting the parallelism they offer remains difficult, especially for legacy application and applications with large serial components. The challenge, then, is to develop techniques ...
Energy efficient speculative threads: dynamic thread allocation in Same-ISA heterogeneous multicore systems
PACT '10: Proceedings of the 19th international conference on Parallel architectures and compilation techniques

Thread-level parallelism at the chip level is critical in overcoming some of the challenges that have been ushered in through the advent of modern multicore processors (CMP). Extracting speculatively parallel threads from sequential applications and ...
Number of Tasks, not Threads, is Key
PDP '15: Proceedings of the 2015 23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing

The concept of task already exists in many parallel programming models. Programmers express parallelism by defining tasks in their applications, and runtime libraries schedule tasks on threads. However, in many task-based parallel programming models, ...

Comments

Information & Contributors

Information

Published In

cover image Guide Proceedings

IPDPS '05: Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 14 - Volume 15

April 2005

ISBN:0769523129

Publisher

IEEE Computer Society

United States

Publication History

Published: 04 April 2005

Qualifiers

Article

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

16
Total Citations
View Citations
0
Total Downloads

Downloads (Last 12 months)0
Downloads (Last 6 weeks)0

Reflects downloads up to 01 Jan 2025

Other Metrics

View Author Metrics

Citations

Cited By

Ghosh SCuevas MCampanoni SDinda PCuicchi CQualters IKramer W(2020)Compiler-based timing for extremely fine-grain preemptive parallelismProceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis10.5555/3433701.3433771(1-15)Online publication date: 9-Nov-2020
https://dl.acm.org/doi/10.5555/3433701.3433771
Jang CLee JSeo SLee JEidt CHoller ASrinivasan UAmarasinghe S(2012)An automatic code overlaying technique for multicores with explicitly-managed memory hierarchiesProceedings of the Tenth International Symposium on Code Generation and Optimization10.1145/2259016.2259045(219-229)Online publication date: 31-Mar-2012
https://dl.acm.org/doi/10.1145/2259016.2259045
St. John TDennis JGao GGuo MHuang Z(2012)Massively parallel breadth first search using a tree-structured memory modelProceedings of the 2012 International Workshop on Programming Models and Applications for Multicores and Manycores10.1145/2141702.2141715(115-123)Online publication date: 26-Feb-2012
https://dl.acm.org/doi/10.1145/2141702.2141715
Nan YLei YDong-rui F(2011)An efficient and flexible task management for many coresTransactions on High-Performance Embedded Architectures and Compilers IV10.5555/2172445.2172463(294-310)Online publication date: 1-Jan-2011
https://dl.acm.org/doi/10.5555/2172445.2172463
Yan YChatterjee SOrozco DGarcia EBudimlić ZShirako JPavel RGao GSarkar V(2011)Hardware and software tradeoffs for task synchronization on manycore architecturesProceedings of the 17th international conference on Parallel processing - Volume Part II10.5555/2033408.2033423(112-123)Online publication date: 29-Aug-2011
https://dl.acm.org/doi/10.5555/2033408.2033423
Ributzka JHayashi YManzano JGao GLowenthal Dde Supinski BMcKee S(2011)The elephant and the miceProceedings of the international conference on Supercomputing10.1145/1995896.1995948(338-347)Online publication date: 31-May-2011
https://dl.acm.org/doi/10.1145/1995896.1995948
Venetis IGao GJohnson GTrinitis CGaydadjiev GVeidenbaum A(2009)Mapping the LU decomposition on a many-core architectureProceedings of the 6th ACM conference on Computing frontiers10.1145/1531743.1531756(71-80)Online publication date: 18-May-2009
https://dl.acm.org/doi/10.1145/1531743.1531756
Guo JLai MPang ZHuang LChen FDai KWang ZWainwright RHaddad H(2008)Hierarchical memory system design for a heterogeneous multi-core processorProceedings of the 2008 ACM symposium on Applied computing10.1145/1363686.1364039(1504-1508)Online publication date: 16-Mar-2008
https://dl.acm.org/doi/10.1145/1363686.1364039
Tan GSreedhar VGao G(2008)Just-In-Time Locality and Percolation for Optimizing Irregular Applications on a Manycore ArchitectureLanguages and Compilers for Parallel Computing10.1007/978-3-540-89740-8_23(331-342)Online publication date: 28-Nov-2008
https://dl.acm.org/doi/10.1007/978-3-540-89740-8_23
Tan GSun NGao GGibbons PScheideler C(2007)A parallel dynamic programming algorithm on a multi-core architectureProceedings of the nineteenth annual ACM symposium on Parallel algorithms and architectures10.1145/1248377.1248399(135-144)Online publication date: 9-Jun-2007
https://dl.acm.org/doi/10.1145/1248377.1248399
Show More Cited By

View Options

View options

Media

Figures

Other

Tables

View Table of Contents