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- research-articleNovember 2023
A Low-Power Artificial-Intelligence-Based 3-D Rendering Processor With Hybrid Deep Neural Network Computing
IEEE Micro (IMIC), Volume 44, Issue 1Pages 17–27https://doi.org/10.1109/MM.2023.3328965A low-power artificial intelligence (AI)-based 3-D rendering processor is proposed for metaverse solutions in mobile platforms. It suggests a brain-inspired rendering acceleration architecture designed with a visual perception core. It removes useless ...
- research-articleNovember 2021
Evolution of the Graphics Processing Unit (GPU)
IEEE Micro (IMIC), Volume 41, Issue 6Pages 42–51https://doi.org/10.1109/MM.2021.3113475Graphics processing units (GPUs) power today’s fastest supercomputers, are the dominant platform for deep learning, and provide the intelligence for devices ranging from self-driving cars to robots and smart cameras. They also generate compelling ...
- research-articleJuly 2015
Scalable Heterogeneous CPU-GPU Computations for Unstructured Tetrahedral Meshes
IEEE Micro (IMIC), Volume 35, Issue 4Pages 6–15https://doi.org/10.1109/MM.2015.70A recent trend in modern high-performance computing environments is the introduction of powerful, energy-efficient hardware accelerators such as GPUs and Xeon Phi coprocessors. These specialized computing devices coexist with CPUs and are optimized for ...
- research-articleJanuary 2009
Larrabee: A Many-Core x86 Architecture for Visual Computing
- Larry Seiler,
- Doug Carmean,
- Eric Sprangle,
- Tom Forsyth,
- Pradeep Dubey,
- Stephen Junkins,
- Adam Lake,
- Robert Cavin,
- Roger Espasa,
- Ed Grochowski,
- Toni Juan,
- Michael Abrash,
- Jeremy Sugerman,
- Pat Hanrahan
IEEE Micro (IMIC), Volume 29, Issue 1Pages 10–21https://doi.org/10.1109/MM.2009.9The Larrabee many-core visual computing architecture uses multiple in-order x86 cores augmented by wide vector processor units, together with some fixed-function logic. This increases the architecture's programmability as compared to standard GPUs. The ...
- research-articleJuly 2008
Parallel Computing Experiences with CUDA
- Michael Garland,
- Scott Le Grand,
- John Nickolls,
- Joshua Anderson,
- Jim Hardwick,
- Scott Morton,
- Everett Phillips,
- Yao Zhang,
- Vasily Volkov
IEEE Micro (IMIC), Volume 28, Issue 4Pages 13–27https://doi.org/10.1109/MM.2008.57The CUDA programming model provides a straightforward means of describing inherently parallel computations, and NVIDIA's Tesla GPU architecture delivers high computational throughput on massively parallel problems. This article surveys experiences ...
- research-articleMarch 2008
NVIDIA Tesla: A Unified Graphics and Computing Architecture
IEEE Micro (IMIC), Volume 28, Issue 2Pages 39–55https://doi.org/10.1109/MM.2008.31To enable flexible, programmable graphics and high-performance computing, NVIDIA has developed the Tesla scalable unified graphics and parallel computing architecture. Its scalable parallel array of processors is massively multithreaded and programmable ...
- research-articleMarch 2005
The GeForce 6800
IEEE Micro (IMIC), Volume 25, Issue 2Pages 41–51https://doi.org/10.1109/MM.2005.37Graphics processing units (GPUs) continue to take on increasing computational workloads and today support interactive rendering that approaches cinematic quality. The architectural drivers for GPUs are programmability, parallelism, bandwidth, and memory ...
- research-articleSeptember 2002
A Polymorphous Computing Fabric
IEEE Micro (IMIC), Volume 22, Issue 5Pages 56–68https://doi.org/10.1109/MM.2002.1044300A new computing fabric is well suited to digital signal processing and image processing applications. The authors describe its implementation on a system on a programmable chip.
