Virtualization is a key technology used in a wide range of applications, from cloud computing to embedded systems. Over the last few years, mainstream computer architectures were extended with hardware virtualization support, giving rise to a set of ...

By analyzing the fault behaviors of conventional flash memory fault models, two new concise fault types are proposed: the 1-safe fault and the 0-safe fault. For a 1(0)-safe fault, if logic 1(0) is programmed into the faulty cell, the effect of the fault ...

This article presents a new fault analysis technique against cryptographic devices called the incremental fault analysis (IFA), which can be adapted into fault attacks using more traditional differential fault analysis (DFA) techniques in order to ...

The open-source RISC-V instruction set architecture (ISA) is gaining traction, both in industry and academia. The ISA is designed to scale from microcontrollers to server-class processors. Furthermore, openness promotes the availability of various open-...

Current multicore platforms contain different types of cores, organized in clusters (e.g., ARM’s big.LITTLE). These platforms deal with concurrently executing applications, having varying workload profiles and performance requirements. Runtime ...

Power capping techniques based on dynamic voltage and frequency scaling (DVFS) and power gating (PG) are oriented toward power actuation, compromising on performance and energy. Inherent error resilience of emerging application domains, such as Internet-...

In this paper, we propose a new energy and lifetime optimization techniques for emerging dark silicon manycore microprocessors considering both hard long-term reliability effects (hard errors) and transient soft errors, which have been studied less in the ...

In this paper, a dynamic on-chip power delivery system for chip multiprocessors (CMPs) is proposed, analogous to the smart grid deployed for large-scale energy distribution. The system includes underprovisioned on-chip voltage regulators (VRs) ...

Software-based self-test (SBST) is an effective method to detect operational faults of a processor system. We propose an architectural approach to support high fault-coverage online SBST: Processor Shield, which tackles the difficult-to-test issues raised ...

This paper studies the problem of maximizing multicore system lifetime reliability, an important design consideration for many real-time embedded systems. Existing work has investigated the problem, but has neglected important failure mechanisms. ...

QR decomposition (QRD) has been a vital component in the transceiver processor of future multiple-input multiple-output (MIMO) systems, in which antenna configuration will be more and more flexible. Therefore, the QRD hardware architecture in the future ...

With technology down scaling, static power has become one of the biggest challenges in a system on chip. Normally off computing using nonvolatile (NV) sequential elements is a promising solution to address this challenge. Recently, many NV shadow flip-...

We propose a cache architecture using a 7T/14T SRAM (Fujiwara <italic>et al.</italic>, 2009) and a control mechanism for reliability enhancements. Our control mechanism differs from conventional dynamic voltage-frequency scaling (DVFS) methods in that it ...

Power management of networked many-core systems with runtime application mapping becomes more challenging in the dark silicon era. It necessitates considering network characteristics at runtime to achieve better performance while honoring the peak power ...

Reconfigurable processors with fine-grained runtime-reconfigurable fabrics are used to speed up applications from different domains. Such a reconfigurable fabric allows loading of application-specific accelerators, where multiple accelerators can be ...

In network-on-chip (NoC)-based systems, performance enhancement has primarily focused on the network itself, with little attention paid on controlling traffic injection at the network boundary. This is unsatisfactory because traffic may be over injected,...

Next-generation chip multiprocessors will require communication performance levels that cannot be achieved by traditional electronic ON-chip interconnects. Silicon photonics has recently emerged as a promising alternative to handle future communication ...

To increase the performance of chip multiprocessors, optical network-on-chip (ONoC) becomes promising because of its high bandwidth and low energy consumption. In this paper, we propose an architecture called RPNoC (Ring-based Packet-switched NoC), ...

The scaling of integrated circuits into the nanometer regime has led to variations emerging as a primary design concern. Most efforts in the area of variation-tolerant design have focused on the physical, circuit, and logic levels of abstraction. ...

Companies operating large datacenters are focusing on how to reduce the electrical energy costs of operating datacenters. A common way of cost reduction is to perform a dynamic voltage and frequency scaling (DVFS), thereby matching the CPU&#x2019;s ...