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Predictive Thermal Management for Energy-Efficient Execution of Concurrent Applications on Heterogeneous Multicores

Published: 01 June 2019 Publication History

Abstract

Current multicore platforms contain different types of cores, organized in clusters (e.g., ARM’s big.LITTLE). These platforms deal with concurrently executing applications, having varying workload profiles and performance requirements. Runtime management is imperative for adapting to such performance requirements and workload variabilities and to increase energy and temperature efficiency. Temperature has also become a critical parameter since it affects reliability, power consumption, and performance and, hence, must be managed. This paper proposes an accurate temperature prediction scheme coupled with a runtime energy management approach to proactively avoid exceeding temperature thresholds while maintaining performance targets. Experiments show up to 20% energy savings while maintaining high-temperature averages and peaks below the threshold. Compared with state-of-the-art temperature predictors, this paper predicts 35% faster and reduces the mean absolute error from 3.25 to 1.15 °C for the evaluated applications’ scenarios.

References

[1]
A. M. Rahmani, M. H. Haghbayan, A. Miele, P. Liljeberg, A. Jantsch, and H. Tenhunen, “Reliability-aware runtime power management for many-core systems in the dark silicon era,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 25, no. 2, pp. 427–440, Feb. 2017.
[2]
Y. G. Kim, M. Kim, and S. W. Chung, “Enhancing energy efficiency of multimedia applications in heterogeneous mobile multi-core processors,” IEEE Trans. Comput., vol. 66, no. 11, pp. 1878–1889, Nov. 2017.
[3]
S. Yanget al., “Adaptive energy minimization of embedded heterogeneous systems using regression-based learning,” in Proc. Int. Workshop Power Timing Modeling, Optim. Simulation, Sep. 2015, pp. 103–110.
[4]
A. K. Coskun, T. S. Rosing, and K. Whisnant, “Temperature aware task scheduling in MPSoCs,” in Proc. EDAA, Apr. 2007, pp. 1–6.
[5]
A. Das, B. Al-Hashimi, and G. V. Merrett, “Adaptive and hierarchical runtime manager for energy-aware thermal management of embedded systems,” ACM Trans. Embedded Comput. Syst., vol. 15, no. 2, p. 24, 2016.
[6]
(2016). Exynos 5 Octa 5422. [Online]. Available: http://www.samsung.com/exynos/
[7]
A. Pathania, Q. Jiao, A. Prakash, and T. Mitra, “Integrated CPU-GPU power management for 3D mobile games,” in Proc. 51st ACM/EDAC/IEEE Design Autom. Conf. (DAC), Jun. 2014, pp. 1–6.
[8]
K. R. Basireddy, A. K. Singh, D. Biswas, G. V. Merrett, and B. M. Al-Hashimi, “Inter-cluster thread-to-core mapping and DVFS on heterogeneous multi-cores,” IEEE Trans. Multi-Scale Comput. Syst., vol. 4, no. 3, pp. 369–382, Jul. 2018.
[9]
K. R. Basireddy, A. Singh, G. V. Merrett, and B. M. Al-Hashimi, “ITMD: Run-time management of concurrent multi-threaded applications on heterogeneous multi-cores,” in Proc. Conf. Design, Autom. Test Eur. (DATE), Jan. 2017, p. 1.
[10]
C. Bienia, S. Kumar, J. P. Singh, and K. Li, “The PARSEC benchmark suite: Characterization and architectural implications,” Princeton Univ., Princeton, NJ, USA, Tech. Rep. TR-811-08, 2008.
[11]
A. Prakash, H. Amrouch, M. Shafique, T. Mitra, and J. Henkel, “Improving mobile gaming performance through cooperative CPU-GPU thermal management,” in Proc. Design Autom. Conf. (DAC), Jun. 2016, p. 47.
[12]
A. K. Coskun, T. S. Rosing, and K. Gross, “Utilizing predictors for efficient thermal management in multiprocessor SoCs,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 28, no. 10, pp. 1503–1516, Oct. 2009.
[13]
L. Ljung, System Identification: Theory for the User, 2nd ed. Upper Saddle River, NJ, USA: Prentice-Hal, 1999.
[14]
Y. Ge, Q. Qiu, and Q. Wu, “A multi-agent framework for thermal aware task migration in many-core systems,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 20, no. 10, pp. 1758–1771, Oct. 2010.
[15]
G. Singla, G. Kaur, A. K. Unver, and U. Y. Ogras, “Predictive dynamic thermal and power management for heterogeneous mobile platforms,” in Proc. Design Autom. Test Eur. Conf., Mar. 2015, pp. 960–965.
[16]
G. Bhat, G. Singla, A. K. Unver, and U. Y. Ogras, “Algorithmic optimization of thermal and power management for heterogeneous mobile platforms,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 26, no. 3, pp. 544–557, Mar. 2018.
[17]
N. Peters, D. Füß, S. Park, and S. Chakraborty, “Frame-based and thread-based power management for mobile games on HMP platforms,” in Proc. IEEE 34th Int. Conf. Comput. Design (ICCD), Oct. 2016, pp. 169–176.
[18]
S. Pagani, H. Khdr, J.-J. Chen, M. Shafique, M. Li, and J. Henkel, “Thermal safe power (TSP): Efficient power budgeting for heterogeneous manycore systems in dark silicon,” IEEE Trans. Comput., vol. 66, no. 1, pp. 147–162, Jan. 2017.
[19]
G. Bhat, S. Gumussoy, and U. Y. Ogras, “Power-temperature stability and safety analysis for multiprocessor systems,” ACM Trans. Embed. Comput. Syst., vol. 16, no. 5s, pp. 145:1–145:19, 2017. [Online]. Available: http://doi.acm.org/10.1145/3126567
[20]
A. Weissel and F. Bellosa, “Process cruise control: Event-driven clock scaling for dynamic power management,” in Proc. Int. Conf. Compil., Archit., Synthesis Embedded Syst. (CASES), 2002, pp. 238–246.
[21]
L. C. Singleton, C. Poellabauer, and K. Schwan, “Monitoring of cache miss rates for accurate dynamic voltage and frequency scaling,” Proc. SPIE, vol. 5680, pp. 121–125, Jan. 2005.
[22]
V. Spiliopoulos, G. Keramidas, S. Kaxiras, and K. Efstathiou, “Power-performance adaptation in Intel core i7,” in Proc. 2nd Workshop Comput. Archit. Oper. Syst. Co-Design, 2011, pp. 1–10.
[23]
A. Nabina and J. L. Nunez-Yanez, “Adaptive voltage scaling in a dynamically reconfigurable FPGA-based platform,” ACM Trans. Reconfigurable Technol. Syst., vol. 5, no. 4, p. 20, 2012.
[24]
A. K. Singh, C. Leech, K. R. Basireddy, B. M. Al-Hashimi, and G. V. Merrett, “Learning-based run-time power and energy management of multi/many-core systems: Current and future trends,” J. Low Power Electron., vol. 13, no. 3, pp. 310–325, Sep. 2017.
[25]
R. A. Shafik, S. Yang, A. Das, L. A. Maeda-Nunez, G. V. Merrett, and B. M. Al-Hashimi, “Learning transfer-based adaptive energy minimization in embedded systems,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 35, no. 6, pp. 877–890, Aug. 2016.
[26]
R. Cochran, C. Hankendi, A. K. Coskun, and S. Reda, “Pack & cap: Adaptive DVFS and thread packing under power caps,” in Proc. 44th Annu. IEEE/ACM Int. Symp. Microarchitecture, Dec. 2011, pp. 175–185.
[27]
H. Sasaki, S. Imamura, and K. Inoue, “Coordinated power-performance optimization in manycores,” in Proc. 22nd Int. Conf. Parallel Archit. Compilation Techn. (PACT), Oct. 2013, pp. 51–61.
[28]
K. V. Craeynest, A. Jaleel, L. Eeckhout, P. Narvaez, and J. Emer, “Scheduling heterogeneous multi-cores through performance impact estimation (PIE),” ACM SIGARCH Comput. Archit. News, vol. 40, no. 3, pp. 213–224, 2012.
[29]
A. Aalsaud, R. Shafik, A. Rafiev, F. Xia, S. Yang, and A. Yakovlev, “Power–aware performance adaptation of concurrent applications in heterogeneous many-core systems,” in Proc. Int. Symp. Low Power Electron. Design, 2016, pp. 368–373.
[30]
J. Ma, G. Yan, Y. Han, and X. Li, “An analytical framework for estimating scale-out and scale-up power efficiency of heterogeneous manycores,” IEEE Trans. Comput., vol. 65, no. 2, pp. 367–381, Feb. 2016.
[31]
E. Del Sozzo, G. C. Durelli, E. Trainiti, A. Miele, M. D. Santambrogio, and C. Bolchini, “Workload-aware power optimization strategy for asymmetric multiprocessors,” in Proc. Design, Autom. Test Eur. Conf. Exhib. (DATE), Mar. 2016, pp. 531–534.
[32]
B. Donyanavard, T. Mück, S. Sarma, and N. Dutt, “SPARTA: Runtime task allocation for energy efficient heterogeneous manycores,” in Proc. 11th IEEE/ACM/IFIP Int. Conf. Hardw./Softw. Codesign Syst. Synthesis, Oct. 2016, pp. 1–10.
[33]
S. C. Woo, M. Ohara, E. Torrie, J. P. Singh, and A. Gupta, “The SPLASH-2 programs: Characterization and methodological considerations,” in Proc. 22nd Annu. Int. Symp. Comput. Archit., 1995, pp. 24–36.
[34]
K. Yu, D. Han, C. Youn, S. Hwang, and J. Lee, “Power-aware task scheduling for big. LITTLE mobile processor,” in Proc. Int. SoC Design Conf. (ISOCC), Nov. 2013, pp. 208–212.
[35]
V. Pallipadi and A. Starikovskiy, “The ondemand governor,” in Proc. Linux Symp., vol. 2, 2006, pp. 215–230.
[36]
[37]
F. Zanini, C. N. Jones, D. Atienza, and G. De Micheli, “Multicore thermal management using approximate explicit model predictive control,” in Proc. Int. Symp. Circuits Syst. (ISCAS), May 2010, pp. 3321–3324.

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        cover image IEEE Transactions on Very Large Scale Integration (VLSI) Systems
        IEEE Transactions on Very Large Scale Integration (VLSI) Systems  Volume 27, Issue 6
        June 2019
        246 pages

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        United States

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        Published: 01 June 2019

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