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- research-article
Minor-embedding heuristics for large-scale annealing processors with sparse hardware graphs of up to 102,400 nodes
- Yuya Sugie,
- Yuki Yoshida,
- Normann Mertig,
- Takashi Takemoto,
- Hiroshi Teramoto,
- Atsuyoshi Nakamura,
- Ichigaku Takigawa,
- Shin-ichi Minato,
- Masanao Yamaoka,
- Tamiki Komatsuzaki
February 2021Soft Computing - A Fusion of Foundations, Methodologies and Applications, Volume 25, Issue 3https://doi.org/10.1007/s00500-020-05502-6 - research-article
CMOS Annealing Machine: A Domain-Specific Architecture for Combinatorial Optimization Problem
January 2020ASPDAC '20: Proceedings of the 25th Asia and South Pacific Design Automation Conferencehttps://doi.org/10.1109/ASP-DAC47756.2020.9045326 - Article
Graph Minors from Simulated Annealing for Annealing Machines with Sparse Connectivity
- Yuya Sugie,
- Yuki Yoshida,
- Normann Mertig,
- Takashi Takemoto,
- Hiroshi Teramoto,
- Atsuyoshi Nakamura,
- Ichigaku Takigawa,
- Shin-Ichi Minato,
- Masanao Yamaoka,
- Tamiki Komatsuzaki
December 2018Theory and Practice of Natural Computinghttps://doi.org/10.1007/978-3-030-04070-3_9 - Article
An Accelerator Chip for Ground-State Searches of the Ising Model with Asynchronous Random Pulse Distribution
December 2015CANDAR '15: Proceedings of the 2015 Third International Symposium on Computing and Networking (CANDAR)https://doi.org/10.1109/CANDAR.2015.64 - Article
Low-voltage limitations of deep-sub-100-nm CMOS LSIs: view of memory designers
March 2007GLSVLSI '07: Proceedings of the 17th ACM Great Lakes symposium on VLSIhttps://doi.org/10.1145/1228784.1228789