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- research-articleApril 2024
FEASTA: A Flexible and Efficient Accelerator for Sparse Tensor Algebra in Machine Learning
- Kai Zhong,
- Zhenhua Zhu,
- Guohao Dai,
- Hongyi Wang,
- Xinhao Yang,
- Haoyu Zhang,
- Jin Si,
- Qiuli Mao,
- Shulin Zeng,
- Ke Hong,
- Genghan Zhang,
- Huazhong Yang,
- Yu Wang
ASPLOS '24: Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 3Pages 349–366https://doi.org/10.1145/3620666.3651336Recently, sparse tensor algebra (SpTA) plays an increasingly important role in machine learning. However, due to the unstructured sparsity of SpTA, the general-purpose processors (e.g., GPU and CPU) are inefficient because of the underutilized hardware ...
- research-articleJanuary 2024
Heterogeneous Instruction Set Architecture for RRAM-enabled In-memory Computing
NANOARCH '23: Proceedings of the 18th ACM International Symposium on Nanoscale ArchitecturesArticle No.: 7, Pages 1–6https://doi.org/10.1145/3611315.3633244RRAM-enabled in-memory computing (IMC) is regarded as a promising solution for breaking the von Neumann bottleneck. Using RRAM-based IMC to construct heterogeneous computing systems can fully leverage the advantages of both digital and IMC platforms. ...
ISA-Grid: Architecture of Fine-grained Privilege Control for Instructions and Registers
ISCA '23: Proceedings of the 50th Annual International Symposium on Computer ArchitectureArticle No.: 15, Pages 1–15https://doi.org/10.1145/3579371.3589050Isolation is a critical mechanism for enhancing the security of computer systems. By controlling the access privileges of software and hardware resources, isolation mechanisms can decouple software into multiple isolated components and enforce the ...
- research-articleJune 2023
Facilitating the Bootstrapping of a New ISA
LCTES 2023: Proceedings of the 24th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded SystemsPages 2–12https://doi.org/10.1145/3589610.3596282Implementation of a new instruction set architecture (ISA) is a non-trivial task that involves significant modifications to the system software, such as the compiler, the assembler, and the linker. This task also includes modifying and verifying ...
- research-articleMarch 2023
RansomShield: A Visualization Approach to Defending Mobile Systems Against Ransomware
ACM Transactions on Privacy and Security (TOPS), Volume 26, Issue 3Article No.: 27, Pages 1–30https://doi.org/10.1145/3579822The unprecedented growth in mobile systems has transformed the way we approach everyday computing. Unfortunately, the emergence of a sophisticated type of malware known as ransomware poses a great threat to consumers of this technology. Traditional ...
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- research-articleFebruary 2023
A Sound and Complete Algorithm for Code Generation in Distance-Based ISA
CC 2023: Proceedings of the 32nd ACM SIGPLAN International Conference on Compiler ConstructionPages 73–84https://doi.org/10.1145/3578360.3580263The single-thread performance of a processor core is essential even in the multicore era. However, increasing the processing width of a core to improve the single-thread performance leads to a super-linear increase in power consumption. To overcome ...
- research-articleJune 2022
Calipers: a criticality-aware framework for modeling processor performance
ICS '22: Proceedings of the 36th ACM International Conference on SupercomputingArticle No.: 2, Pages 1–14https://doi.org/10.1145/3524059.3532390Computer architecture design space is vast and complex. Tools are needed to explore new ideas and gain insights quickly, at low effort and desired accuracy. Cycle Accurate Simulators (CAS), commonly used to explore computer designs, can be slow and ...
- research-articleMay 2022
Design and evaluation frameworks for advanced RISC-based ternary processor
DATE '22: Proceedings of the 2022 Conference & Exhibition on Design, Automation & Test in EuropePages 1077–1082In this paper, we introduce the design and verification frameworks for developing a fully-functional emerging ternary processor. Based on the existing compiling environments for binary processors, for the given ternary instructions, the software-level ...
- research-articleJanuary 2022
Design and implementation of an ASIP for SHA-3 hash algorithm
International Journal of Information and Computer Security (IJICS), Volume 17, Issue 3-4Pages 285–309https://doi.org/10.1504/ijics.2022.122375In recent years, application specific instruction set processor (ASIP) has attracted many researchers attention. These processors resemble application specific integrated circuits (ASICs) and digital signal processors (DSPs) from the performance and ...
- research-articleNovember 2021
Designing calibration and expressivity-efficient instruction sets for quantum computing
ISCA '21: Proceedings of the 48th Annual International Symposium on Computer ArchitecturePages 846–859https://doi.org/10.1109/ISCA52012.2021.00071Near-term quantum computing (QC) systems have limited qubit counts, high gate (instruction) error rates, and typically support a minimal instruction set having one type of two-qubit gate (2Q). To reduce program instruction counts and improve application ...
- research-articleNovember 2020
Designing and evaluating new instructions that accelerate sigmoid-based machine learning
CASCON '20: Proceedings of the 30th Annual International Conference on Computer Science and Software EngineeringPages 189–197Activation functions (such as sigmoid and tanh) are an expensive operation in the neural network algorithms used in deep learning. Previous work has investigated different ways of accelerating the table lookup and exceptional-branch handling involved in ...
- research-articleOctober 2020
Formal Verification of Spacecraft Control Programs
ACM Transactions on Embedded Computing Systems (TECS), Volume 19, Issue 5Article No.: 37, Pages 1–18https://doi.org/10.1145/3391900Verification of correctness of control programs is an essential task in the development of space electronics; it is difficult and typically outweighs design and programming tasks in terms of development hours. This article presents a verification ...
- research-articleDecember 2019
A Metric-Guided Method for Discovering Impactful Features and Architectural Insights for Skylake-Based Processors
ACM Transactions on Architecture and Code Optimization (TACO), Volume 16, Issue 4Article No.: 46, Pages 1–25https://doi.org/10.1145/3369383The slowdown in technology scaling puts architectural features at the forefront of the innovation in modern processors. This article presents a Metric-Guided Method (MGM) that extends Top-Down analysis with carefully selected, dynamically adapted ...
- research-articleDecember 2019
A case against indirect jumps for secure programs
SSPREW9 '19: Proceedings of the 9th Workshop on Software Security, Protection, and Reverse EngineeringArticle No.: 3, Pages 1–10https://doi.org/10.1145/3371307.3371314A desired property of secure programs is control flow integrity (CFI): an attacker must not be able to alter how instructions are chained as specified in the program. Numerous techniques try to achieve this property with various trade-offs. But to ...
- research-articleAugust 2019
Formal verification of spacecraft control programs (experience report)
Haskell 2019: Proceedings of the 12th ACM SIGPLAN International Symposium on HaskellPages 139–145https://doi.org/10.1145/3331545.3342593Verification of correctness of control programs is an essential task in the development of space electronics; it is difficult and typically outweighs design and programming tasks in terms of development hours. This experience report presents a ...
- short-paperNovember 2018
xBGAS: Toward a RISC-V ISA Extension for Global, Scalable Shared Memory
MCHPC'18: Proceedings of the Workshop on Memory Centric High Performance ComputingPages 22–26https://doi.org/10.1145/3286475.3286478Given the switch from monolithic architectures to integrated systems of commodity components, scalable high performance computing architectures often suffer from unwanted latencies when operations depart an individual device domain. Transferring control ...
- research-articleOctober 2018
Hardware/software codesign for mathematical function acceleration
CASCON '18: Proceedings of the 28th Annual International Conference on Computer Science and Software EngineeringPages 168–177Many important workloads depend on the efficient computation of elementary functions like square root and logarithm. Accurate computation of these functions is time-consuming, and hard for compilers to schedule, because of conditional execution. These ...
- research-articleJune 2018
Power-based side-channel instruction-level disassembler
DAC '18: Proceedings of the 55th Annual Design Automation ConferenceArticle No.: 119, Pages 1–6https://doi.org/10.1145/3195970.3196094Modern embedded computing devices are vulnerable against malware and software piracy due to insufficient security scrutiny and the complications of continuous patching. To detect malicious activity as well as protecting the integrity of executable ...
- research-articleOctober 2017
Unbounded superoptimization
Onward! 2017: Proceedings of the 2017 ACM SIGPLAN International Symposium on New Ideas, New Paradigms, and Reflections on Programming and SoftwarePages 78–88https://doi.org/10.1145/3133850.3133856Our aim is to enable software to take full advantage of the capabilities of emerging microprocessor designs without modifying the compiler.
Towards this end, we propose a new approach to code generation and optimization. Our approach uses an SMT ...
- research-articleApril 2017
Typed Architectures: Architectural Support for Lightweight Scripting
- Channoh Kim,
- Jaehyeok Kim,
- Sungmin Kim,
- Dooyoung Kim,
- Namho Kim,
- Gitae Na,
- Young H. Oh,
- Hyeon Gyu Cho,
- Jae W. Lee
ASPLOS '17: Proceedings of the Twenty-Second International Conference on Architectural Support for Programming Languages and Operating SystemsPages 77–90https://doi.org/10.1145/3037697.3037726Dynamic scripting languages are becoming more and more widely adopted not only for fast prototyping but also for developing production-grade applications. They provide high-productivity programming environments featuring high levels of abstraction with ...
Also Published in:
ACM SIGPLAN Notices: Volume 52 Issue 4ACM SIGARCH Computer Architecture News: Volume 45 Issue 1