Design and evaluation frameworks for advanced RISC-based ternary processor
Authors: 
Dongyun Kam, Jung Gyu Min, Jongho Yoon, Sunmean Kim, Seokhyeong Kang, Youngjoo LeeAuthors Info & Claims
Dongyun Kam, Jung Gyu Min, Jongho Yoon, Sunmean Kim, Seokhyeong Kang, Youngjoo LeeAuthors Info & ClaimsPages 1077 - 1082
Abstract
In this paper, we introduce the design and verification frameworks for developing a fully-functional emerging ternary processor. Based on the existing compiling environments for binary processors, for the given ternary instructions, the software-level framework provides an efficient way to convert the given programs to the ternary assembly codes. We also present a hardware-level framework to rapidly evaluate the performance of a ternary processor implemented in arbitrary design technology. As a case study, the fully-functional 9-trit advanced RISC-based ternary (ART-9) core is newly developed by using the proposed frameworks. Utilizing 24 custom ternary instructions, the 5-stage ART-9 prototype architecture is successfully verified by a number of test programs including dhrystone benchmark in a ternary domain, achieving the processing efficiency of 57.8 DMIPS/W and 3.06×106 DMIPS/W in the FPGA-level ternary-logic emulations and the emerging CNTFET ternary gates, respectively.
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Published In
March 2022
1637 pages
ISBN:9783981926361
- General Chairs:
- Cristiana Bolchini,
- Ian O'Connor,
- Program Chairs:
- Ingrid Verbauwhede,
- Robert Wille
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- EDAA: European Design Automation Association
- IEEE SSCS Shanghai Chapter
- ESDA: Electronic System Design Alliance
- IEEE CEDA
- IEEE CS
- IEEE-RAS: Robotics and Automation
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European Design and Automation Association
Leuven, Belgium
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Published: 31 May 2022
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