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Traditional NoC’s buffer design mainly bases on SRAM that could not break through the high static power consumption characteristics by itself, which could be solved by emerging NVMs, such as energy-efficient RTM (Racetrack Memory). Using RTM ...$\mathrm{}$

Racetrack memory (RM) is a potential DRAM alternative due to its high density and low energy cost and comparative access latency with SRAM. On this occasion, we propose a shift insensitive racetrack main memory architecture SIRM. SIRM provides ...

The large area and high power consumption are the two main bottlenecks in the conventional SRAM-based Field Programmable Gate Arrays (FPGAs). In recent works, resistive Non-Volatile Memories (NVMs) have been widely proposed to tackle the above ...

• A hybrid LUT with one non-volatile input and multiple volatile inputs.
• The computation and storage are integrated in the non-volatile input.
• The hybrid LUT reduces the area and leakage power with extra reconfigurable resource.
• ...

SRAM based register file (RF) is one of the major factors limiting the scaling of GPGPU. In this work, we propose to use the emerging nonvolatile domain-wall-shift-write based racetrack memory (DWSW-RM) to implement a power-efficient GPGPU RF, of which ...