research-article

Exploration of GPGPU Register File Architecture Using Domain-wall-shift-write based Racetrack Memory

Authors:

Hai (Helen) LiAuthors Info & Claims

DAC '14: Proceedings of the 51st Annual Design Automation Conference

Pages 1 - 6

https://doi.org/10.1145/2593069.2593137

Published: 01 June 2014 Publication History

Abstract

SRAM based register file (RF) is one of the major factors limiting the scaling of GPGPU. In this work, we propose to use the emerging nonvolatile domain-wall-shift-write based racetrack memory (DWSW-RM) to implement a power-efficient GPGPU RF, of which the power consumption is substantially reduced. A holistic technology set is developed to minimize the high access cost of DWSW-RW caused by the sequential access mechanism. Experiment results show that our proposed techniques can improve the GPGPU performance by 4.6% compared to the baseline with SRAM based RF. The RF energy efficiency is also significantly improved by 2.45×.

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Cited By

Guan XZhou HBao GLi HZhu LYao JGrosser TDubach CSteuwer MXue JOttoni GQuintão Pereira F(2024)PresCount: Effective Register Allocation for Bank Conflict ReductionProceedings of the 2024 IEEE/ACM International Symposium on Code Generation and Optimization10.1109/CGO57630.2024.10444841(170-181)Online publication date: 2-Mar-2024
https://dl.acm.org/doi/10.1109/CGO57630.2024.10444841
Khan AHameed FBläsing RParkin SCastrillon J(2019)ShiftsReduceACM Transactions on Architecture and Code Optimization10.1145/337248916:4(1-23)Online publication date: 26-Dec-2019
https://dl.acm.org/doi/10.1145/3372489
Li BMao MLiu XLiu TLiu ZWen WChen YLi H(2019)Thread Batching for High-performance Energy-efficient GPU Memory DesignACM Journal on Emerging Technologies in Computing Systems10.1145/333015215:4(1-21)Online publication date: 16-Dec-2019
https://dl.acm.org/doi/10.1145/3330152
Show More Cited By

Index Terms

Exploration of GPGPU Register File Architecture Using Domain-wall-shift-write based Racetrack Memory
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
      1. Multiple instruction, multiple data

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cover image ACM Other conferences

DAC '14: Proceedings of the 51st Annual Design Automation Conference

June 2014

1249 pages

ISBN:9781450327305

DOI:10.1145/2593069

Copyright © 2014 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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EDAC: Electronic Design Automation Consortium
SIGBED: ACM Special Interest Group on Embedded Systems
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CEDA

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New York, NY, United States

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Published: 01 June 2014

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DAC '14

DAC '14: The 51st Annual Design Automation Conference 2014

June 1 - 5, 2014

CA, San Francisco, USA

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

Guan XZhou HBao GLi HZhu LYao JGrosser TDubach CSteuwer MXue JOttoni GQuintão Pereira F(2024)PresCount: Effective Register Allocation for Bank Conflict ReductionProceedings of the 2024 IEEE/ACM International Symposium on Code Generation and Optimization10.1109/CGO57630.2024.10444841(170-181)Online publication date: 2-Mar-2024
https://dl.acm.org/doi/10.1109/CGO57630.2024.10444841
Khan AHameed FBläsing RParkin SCastrillon J(2019)ShiftsReduceACM Transactions on Architecture and Code Optimization10.1145/337248916:4(1-23)Online publication date: 26-Dec-2019
https://dl.acm.org/doi/10.1145/3372489
Li BMao MLiu XLiu TLiu ZWen WChen YLi H(2019)Thread Batching for High-performance Energy-efficient GPU Memory DesignACM Journal on Emerging Technologies in Computing Systems10.1145/333015215:4(1-21)Online publication date: 16-Dec-2019
https://dl.acm.org/doi/10.1145/3330152
Liang ZSun GKang WChen XZhao W(2019)ZUMAProceedings of the 56th Annual Design Automation Conference 201910.1145/3316781.3317937(1-6)Online publication date: 2-Jun-2019
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Aghaei Khouzani HYang CHomayoun HTaskin BMohsenin TZhao W(2019)Tuning Track-based NVM Caches for Low-Power IoT DevicesProceedings of the 2019 Great Lakes Symposium on VLSI10.1145/3299874.3319335(513-518)Online publication date: 13-May-2019
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Chen FLi ZKang WZhao WLi HChen YShin Y(2018)Process variation aware data management for magnetic skyrmions racetrack memoryProceedings of the 23rd Asia and South Pacific Design Automation Conference10.5555/3201607.3201653(221-226)Online publication date: 22-Jan-2018
https://dl.acm.org/doi/10.5555/3201607.3201653
Sadrosadati MMirhosseini AEhsani SSarbazi-Azad HDrumond MFalsafi BAusavarungnirun RMutlu O(2018)LTRFACM SIGPLAN Notices10.1145/3296957.317321153:2(489-502)Online publication date: 19-Mar-2018
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Sadrosadati MMirhosseini AEhsani SSarbazi-Azad HDrumond MFalsafi BAusavarungnirun RMutlu OShen XTuck JBianchini RSarkar V(2018)LTRFProceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems10.1145/3173162.3173211(489-502)Online publication date: 19-Mar-2018
https://dl.acm.org/doi/10.1145/3173162.3173211
Luo TZhang WHe BMaskell DParameswaran S(2017)A novel two-stage modular multiplier based on racetrack memory for asymmetric cryptographyProceedings of the 36th International Conference on Computer-Aided Design10.5555/3199700.3199737(276-282)Online publication date: 13-Nov-2017
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Khouzani HFotouhi PYang CGao G(2017)Leveraging access port positions to accelerate page table walk in DWM-based main memoryProceedings of the Conference on Design, Automation & Test in Europe10.5555/3130379.3130720(1454-1459)Online publication date: 27-Mar-2017
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