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- research-articleNovember 2024
TrEnv: Transparently Share Serverless Execution Environments Across Different Functions and Nodes
- Jialiang Huang,
- MingXing Zhang,
- Teng Ma,
- Zheng Liu,
- Sixing Lin,
- Kang Chen,
- Jinlei Jiang,
- Xia Liao,
- Yingdi Shan,
- Ning Zhang,
- Mengting Lu,
- Tao Ma,
- Haifeng Gong,
- YongWei Wu
SOSP '24: Proceedings of the ACM SIGOPS 30th Symposium on Operating Systems PrinciplesPages 421–437https://doi.org/10.1145/3694715.3695967Serverless computing is renowned for its computation elasticity, yet its full potential is often constrained by the requirement for functions to operate within local and dedicated background environments, resulting in limited memory elasticity. To ...
- research-articleNovember 2024JUST ACCEPTED
ShieldCXL: A Practical Obliviousness Support with Sealed CXL Memory
ACM Transactions on Architecture and Code Optimization (TACO), Just Accepted https://doi.org/10.1145/3703354The CXL (Compute Express Link) technology is an emerging memory interface with high-level commands. Recent studies applied the CXL memory expanding technique to mitigate the capacity limitation of the conventional DDRx memory. Unlike the prior studies to ...
- research-articleNovember 2024
Fundamental OS Design Considerations for CXL-based Hybrid SSDs
DIMES '24: Proceedings of the 2nd Workshop on Disruptive Memory SystemsPages 51–59https://doi.org/10.1145/3698783.3699380The first commercial implementations of CXL-based hybrid SSDs (i.e., SSDs that are both byte- and block-addressable) are looming on the horizon. Although previous works have conducted design studies on hardware concepts as well as potential use cases, ...
- research-articleNovember 2024
Lupin: Tolerating Partial Failures in a CXL Pod
DIMES '24: Proceedings of the 2nd Workshop on Disruptive Memory SystemsPages 41–50https://doi.org/10.1145/3698783.3699377A compute express link (CXL) pod is a collection of hosts attached to a CXL memory module. It provides an opportunity to port single-host shared-memory programs to execute on multiple hosts in a CXL pod, where the ported application achieves higher ...
- short-paperDecember 2024
Using Isoefficiency as a Metric to Assess Disaggregated Memory Systems for High Performance Computing
MEMSYS '24: Proceedings of the International Symposium on Memory SystemsPages 192–197https://doi.org/10.1145/3695794.3695812Memory disaggregation is an approach to decouple compute and memory to minimize the total cost of ownership. However, analytical methods to study the impact of this approach are not readily available for high performance computing use cases. In this ...
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- research-articleSeptember 2024
NotNets: Accelerating Microservices by Bypassing the Network
- Peter Alvaro,
- Matthew Adiletta,
- David Cheng,
- Adrian Cockroft,
- Frank Hady,
- Ramesh Illikkal,
- Esteban Ramos,
- Robert Soulé
APSys '24: Proceedings of the 15th ACM SIGOPS Asia-Pacific Workshop on SystemsPages 67–73https://doi.org/10.1145/3678015.3680494Remote procedure calls are the workhorse of distributed systems. However, as software engineering trends, such as micro-services and serverless computing, push applications towards ever finer-grained decompositions, the overhead of RPC-based ...
Yggdrasil: Reducing Network I/O Tax with (CXL-Based) Distributed Shared Memory
ICPP '24: Proceedings of the 53rd International Conference on Parallel ProcessingPages 597–606https://doi.org/10.1145/3673038.3673138In communication-intensive applications that run on hosts with high-speed network hardware, a common challenge arises from the significant burden placed on the native socket system within the OS. Researchers have devoted considerable effort to optimizing ...
- research-articleAugust 2024
Revisiting Learned Index with Byte-addressable Persistent Storage
- Rui Zhang,
- Yukai Huang,
- Sicheng Liang,
- Shangyi Sun,
- Shaonan Ma,
- Chengying Huan,
- Lulu Chen,
- Zhihui Lu,
- Yang Xu,
- Ming Yan,
- Jie Wu
ICPP '24: Proceedings of the 53rd International Conference on Parallel ProcessingPages 929–938https://doi.org/10.1145/3673038.3673113Byte-addressable Persistent Storage (BPS), such as persistent memory and CXL-enabled SSDs, has become an extension of main memory. This opens up new possibilities for indexes that operate and persist data directly on the memory bus. Recent learned ...
- research-articleJuly 2024
OMB-CXL: A Micro-Benchmark Suite for Evaluating MPI Communication Utilizing Compute Express Link Memory Devices
- Tu Tran,
- Mustafa Abduljabbar,
- Hooyoung Ahn,
- Seonyoung Kim,
- Yoomi Park,
- Woojong Han,
- Shinyoung Ahn,
- Hari Subramoni,
- Dhabaleswar K. Panda
PEARC '24: Practice and Experience in Advanced Research Computing 2024: Human Powered ComputingArticle No.: 27, Pages 1–8https://doi.org/10.1145/3626203.3670533Compute Express Link (CXL) is a promising technology providing connectivity between host processors and peripheral devices like accelerators or memory modules. Compute nodes are usually connected through a high-speed network like Ethernet or Infiniband. ...
- research-articleJuly 2024
Breaking Barriers: Expanding GPU Memory with Sub-Two Digit Nanosecond Latency CXL Controller
- Donghyun Gouk,
- Seungkwan Kang,
- Hanyeoreum Bae,
- Eojin Ryu,
- Sangwon Lee,
- Dongpyung Kim,
- Junhyeok Jang,
- Myoungsoo Jung
HotStorage '24: Proceedings of the 16th ACM Workshop on Hot Topics in Storage and File SystemsPages 108–115https://doi.org/10.1145/3655038.3665953This work introduces a GPU storage expansion solution utilizing CXL, featuring a novel GPU system design with multiple CXL root ports for integrating diverse storage media (DRAMs and/or SSDs). We developed and siliconized a custom CXL controller ...
- research-articleJuly 2024
Dictionary Based Cache Line Compression
HotStorage '24: Proceedings of the 16th ACM Workshop on Hot Topics in Storage and File SystemsPages 8–14https://doi.org/10.1145/3655038.3665941Active-standby mechanisms for VM high-availability demand frequent synchronization of memory and CPU state, involving the identification and transfer of "dirty" memory pages to a standby target. Building upon the granularity offered by CXL-enabled memory ...
- tutorialJuly 2024
An Introduction to the Compute Express Link (CXL) Interconnect
ACM Computing Surveys (CSUR), Volume 56, Issue 11Article No.: 290, Pages 1–37https://doi.org/10.1145/3669900The Compute Express Link (CXL) is an open industry-standard interconnect between processors and devices such as accelerators, memory buffers, smart network interfaces, persistent memory, and solid-state drives. CXL offers coherency and memory semantics ...
- research-articleJuly 2024
Tiresias: Optimizing NUMA Performance with CXL Memory and Locality-Aware Process Scheduling
ACM-TURC '24: Proceedings of the ACM Turing Award Celebration Conference - China 2024Pages 6–11https://doi.org/10.1145/3674399.3674411The growing demand for memory systems with larger capacities and faster data transfer speeds has driven progress in the widespread adoption of multi-socket machines and memory expansion through Compute eXpress Link (CXL). However, processes running on ...
DRackSim: Simulating CXL-enabled Large-Scale Disaggregated Memory Systems
- Amit Puri,
- Kartheek Bellamkonda,
- Kailash Narreddy,
- John Jose,
- Venkatesh Tamarapalli,
- Vijaykrishnan Narayanan
SIGSIM-PADS '24: Proceedings of the 38th ACM SIGSIM Conference on Principles of Advanced Discrete SimulationPages 3–14https://doi.org/10.1145/3615979.3656059Memory disaggregation has emerged as an alternative to traditional server architecture in data centers to target better memory utilization and higher scalability. It involves multiple independent compute nodes and remote memory pools that get hardware ...
- research-articleApril 2024
TAROT: A CXL SmartNIC-Based Defense Against Multi-bit Errors by Row-Hammer Attacks
- Chihun Song,
- Michael Jaemin Kim,
- Tianchen Wang,
- Houxiang Ji,
- Jinghan Huang,
- Ipoom Jeong,
- Jaehyun Park,
- Hwayong Nam,
- Minbok Wi,
- Jung Ho Ahn,
- Nam Sung Kim
ASPLOS '24: Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 3Pages 981–998https://doi.org/10.1145/3620666.3651325Row Hammer (RH) has been demonstrated as a security vulnerability in modern systems. Although commodity CPUs can handle RH-induced single-bit errors in DRAM through ECC, RH can still give rise to multi-bit uncorrectable errors (UEs) and crash the ...
- research-articleJanuary 2024
Rcmp: Reconstructing RDMA-Based Memory Disaggregation via CXL
ACM Transactions on Architecture and Code Optimization (TACO), Volume 21, Issue 1Article No.: 15, Pages 1–26https://doi.org/10.1145/3634916Memory disaggregation is a promising architecture for modern datacenters that separates compute and memory resources into independent pools connected by ultra-fast networks, which can improve memory utilization, reduce cost, and enable elastic scaling of ...
- research-articleNovember 2023
CXL Memory as Persistent Memory for Disaggregated HPC: A Practical Approach
SC-W '23: Proceedings of the SC '23 Workshops of The International Conference on High Performance Computing, Network, Storage, and AnalysisPages 983–994https://doi.org/10.1145/3624062.3624175In the landscape of High-Performance Computing (HPC), the quest for efficient and scalable memory solutions remains paramount. The advent of Compute Express Link (CXL) introduces a promising avenue with its potential to function as a Persistent Memory (...
- research-articleNovember 2023
GPU Graph Processing on CXL-Based Microsecond-Latency External Memory
- Shintaro Sano,
- Yosuke Bando,
- Kazuhiro Hiwada,
- Hirotsugu Kajihara,
- Tomoya Suzuki,
- Yu Nakanishi,
- Daisuke Taki,
- Akiyuki Kaneko,
- Tatsuo Shiozawa
SC-W '23: Proceedings of the SC '23 Workshops of The International Conference on High Performance Computing, Network, Storage, and AnalysisPages 962–972https://doi.org/10.1145/3624062.3624173In GPU graph analytics, the use of external memory such as the host DRAM and solid-state drives is a cost-effective approach to processing large graphs beyond the capacity of the GPU onboard memory. This paper studies the use of Compute Express Link (...
- research-articleOctober 2023
Near to Far: An Evaluation of Disaggregated Memory for In-Memory Data Processing
- Andreas Geyer,
- Johannes Pietrzyk,
- Alexander Krause,
- Dirk Habich,
- Wolfgang Lehner,
- Christian Färber,
- Thomas Willhalm
DIMES '23: Proceedings of the 1st Workshop on Disruptive Memory SystemsPages 16–22https://doi.org/10.1145/3609308.3625271Efficient in-memory data processing relies on the availability of sufficient resources, be it CPU time or available main memory. Traditional approaches are coping with resource limitations by either adding more processors or RAM sticks to a single ...
- research-articleOctober 2023
Persistent Memory Research in the Post-Optane Era
- Peter Desnoyers,
- Ian Adams,
- Tyler Estro,
- Anshul Gandhi,
- Geoff Kuenning,
- Mike Mesnier,
- Carl Waldspurger,
- Avani Wildani,
- Erez Zadok
DIMES '23: Proceedings of the 1st Workshop on Disruptive Memory SystemsPages 23–30https://doi.org/10.1145/3609308.3625268After over a decade of researcher anticipation for the arrival of persistent memory (PMem), the first shipments of 3D XPoint-based Intel Optane Memory in 2019 were quickly followed by its cancellation in 2022. Was this another case of an idea quickly ...