2024 Proceeding
- Sponsor:
- sigops
About the Workshop on Disruptive Memory Systems (DIMES) Novel memory types are shattering our decades-old assumptions about the interface between hard- and software. Instead of volatile, passive and largely homogeneous main memory, current systems support non-volatile main memory, hybrid architectures combine classic memory modules with high-bandwidth memory, and disaggregated memory is no longer connected to the processor via the memory bus. In-memory and near-memory computing abandon the traditional von Neumann architecture and enable large numbers of parallel operations with the enormous potential for gains in performance and energy efficiency. The Workshop on Disruptive Memory Systems (DIMES) is a platform to discuss new visions, abstractions, and interfaces that will allow system software to exploit the opportunities of novel memory technologies in existing and future software. Our discussion focuses on system software of all types in various different computing domains (e.g., embedded, edge, cloud, and HPC).
Proceeding Downloads
Performance Models for Task-based Scheduling with Disruptive Memory Technologies
Disruptive memory technologies break out of the memory pyramid and mandate specialized performance models and algorithms for optimal use. While the literature offers various - occasionally conflicting - models for individual technologies, few of these ...
Demystifying Intel Data Streaming Accelerator for In-Memory Data Processing
- André Berthold,
- Constantin Fürst,
- Antonia Obersteiner,
- Lennart Schmidt,
- Dirk Habich,
- Wolfgang Lehner,
- Horst Schirmeier
In-memory data processing is the state-of-the-art approach for large-scale data analytics. For a more efficient processing and to be able to store more data in main memory, new hardware developments for memory such as Compute Express Link (CXL) and High-...
To Keep or Not to Keep - The Volatility of Replacement Policy Metadata in Hybrid Caches
The field of Non-Volatile Memory (NVM) is one of the most actively researched topics regarding disruptive memory technologies. A promising application of NVM lies in the hybridization of caches, combining both NVM and conventional SRAM to realize trade-...
Moses: Heap Partitioning for Semantic Data Tiering
The adoption of emerging memory technologies has long been impeded by the lack of interfaces communicating memory placement semantics not only between applications, system software, and diagnostics tools but also between multiple tenants in a system. ...
The New Costs of Physical Memory Fragmentation
- Alexander Halbuer,
- Illia Ostapyshyn,
- Lukas Steiner,
- Lars Wrenger,
- Matthias Jung,
- Christian Dietrich,
- Daniel Lohmann
External fragmentation is becoming a serious problem again after paging temporarily solved it with its one-size-fits-all 4 KiB approach. The increasing adoption of mixed base, huge, and giant page sizes, DRAM energy-saving techniques, and memory ...
Lupin: Tolerating Partial Failures in a CXL Pod
A compute express link (CXL) pod is a collection of hosts attached to a CXL memory module. It provides an opportunity to port single-host shared-memory programs to execute on multiple hosts in a CXL pod, where the ported application achieves higher ...
Fundamental OS Design Considerations for CXL-based Hybrid SSDs
The first commercial implementations of CXL-based hybrid SSDs (i.e., SSDs that are both byte- and block-addressable) are looming on the horizon. Although previous works have conducted design studies on hardware concepts as well as potential use cases, ...
Novel Memory Technologies for Multi-Tenant Exploratory Programming
The current deep learning trend has given new popularity to the Exploratory Programming style, which often comes with high and exclusive-use demands on compute hardware and memory resources. Yet, the underlying system software is unaware of the memory ...
Index Terms
- Proceedings of the 2nd Workshop on Disruptive Memory Systems
Recommendations
Refresh pausing in DRAM memory systems
Dynamic Random Access Memory (DRAM) cells rely on periodic refresh operations to maintain data integrity. As the capacity of DRAM memories has increased, so has the amount of time consumed in doing refresh. Refresh operations contend with read ...
Write-aware memory management for hybrid SLC-MLC PCM memory systems
In recent years, phase-change memory (PCM) has generated a great deal of interest because of its byte addressability and non-volatility properties. It is regarded as a good alternative storage medium that can reduce the performance gap between the main ...
Acceptance Rates
| Year | Submitted | Accepted | Rate |
|---|---|---|---|
| DIMES '23 | 17 | 8 | 47% |
| Overall | 17 | 8 | 47% |