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NoCArc '12: Proceedings of the Fifth International Workshop on Network on Chip Architectures
ACM2012 Proceeding
Publisher:
  • Association for Computing Machinery
  • New York
  • NY
  • United States
Conference:
NoCArc '12: Fifth International Workshop on Network on Chip Architectures Vancouver British Columbia Canada 1 December 2012
ISBN:
978-1-4503-1540-1
Published:
01 December 2012
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Abstract

The papers in this volume form the proceedings of the 5th International Workshop on Network on Chip Architectures (NoCArc 2012) held on December 1, 2012, in conjunction with the 45th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-45), December 1--5, 2012, Vancouver, BC, Canada.

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keynote
Developing survival instincts in computing systems

Complex information and communication systems have been studied for a long time. Many approaches and methodologies exist to date. Amongst the properties of interest in those studies the prominent place is occupied by the property of systems to stay ...

SESSION: Emerging architectures and technologies
research-article
Network on metachip architectures

The size of systems on a chip is limited by our ability to design and fabricate such systems, staying within the appropriate costs depending on the application. In this paper, we propose a divide-and-conquer approach, Quilt Packaging®, to be utilized ...

research-article
Surface wave communication system for on-chip and off-chip interconnects

Network-on-chip (NoC) is a communication paradigm that has emerged to tackle different on-chip challenges and satisfy different demands in terms of high performance and economical interconnect implementation. However, merely metal based interconnect ...

research-article
A structural analysis of evolved complex networks-on-chip

Designing large-scale heterogeneous Networks-on-Chip (NoCs) for irregular applications often involves sophisticated optimization techniques that lead to unstructured networks. Such networks are hard to understand because they were not built with common ...

SESSION: 3D design
research-article
Power efficiency of wavelength-routed optical NoC topologies for global connectivity of 3D multi-core processors

There is still a significant gap between the optical network-on-chip (NoC) concept and a mature interconnect technology with practical relevance. Current research aims at bridging this gap by evolving basic optical components and by developing ad-hoc ...

research-article
Deadlock-free and plane-balanced adaptive routing for 3D networks-on-chip

This paper proposes a new method for designing adaptive routing algorithms for 3D networks-on-chip (NoCs). This method is based on extending the existing 2D turn model adaptive routing to a 3D scenario. A 3-D plane-balanced approach with maximal degree ...

research-article
A high-efficiency low-cost heterogeneous 3D network-on-chip design

In this paper, we propose and analyze a heterogeneous Three Dimensional (3D) Network-on-Chip (NoC) design based on the optimized placement of vertical connections. NoC paradigm is expected to be the solution of future multicore processors, while 3D NoC ...

SESSION: Arbitration, routing and link design
research-article
Junction based routing: a scalable technique to support source routing in large NoC platforms

To support communication among hundreds of cores on a chip, on-chip communication must be well organized. In the embedded systems using such a chip, the communication patterns can be profiled off-line and routing can be well planned. Source routing has ...

research-article
Position-based weighted round-robin arbitration for equality of service in many-core network-on-chips

This paper presents the position-based weighted round-robin arbitration for equality of service in many-core network-on-chips employing a deterministic routing algorithm. We concentrate on the network saturation induced by the hot-spot traffic that ...

research-article
Variability-tolerant NoC link design

In this paper we propose a model for the design of Networks-on-Chip (NoC) links that takes into considerations the systematic and random effects of process variability. The model predicts the delay variations of each NoC link in a floor-plan. Delay ...

research-article
Low power flitwise routing in an unidirectional torus with minimal buffering

State-of-the-art Network on Chips (NoCs) provide a high throughput and low latency by sending packets of data through a mesh topology, using virtual channels and wormhole flow control. The downside of this technology is a high area and energy ...

Contributors
  • University of Catania
  • University of Southampton

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Acceptance Rates

Overall Acceptance Rate 46 of 122 submissions, 38%
YearSubmittedAcceptedRate
NoCArc '2314536%
NoCArc '219556%
NoCArc '1916744%
NoCArc '1720630%
NoCArc '1620840%
NoCArc '1521629%
NoCArc '1422941%
Overall1224638%