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PLUS: a distributed shared-memory system

Authors:

Roberto Bisiani,

Mosur RavishankarAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 18, Issue 2SI

Pages 115 - 124

https://doi.org/10.1145/325096.325121

Published: 01 May 1990 Publication History

Abstract

PLUS is a multiprocessor architecture tailored to the fast execution of a single multithreaded process; its goal is to accelerate the execution of CPU-bound applications. PLUS supports shared memory and efficient synchronization. Memory access latency is reduced by non-demand replication of pages with hardware-supported coherence between replicated pages. The architecture has been simulated in detail and the paper presents some of the key measurements that have been used to substantiate our architectural decisions. The current implementation of PLUS is also described.

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Cited By

Gelado IStone JCabezas JPatel SNavarro NHwu WHoe JAdve V(2010)An asymmetric distributed shared memory model for heterogeneous parallel systemsProceedings of the fifteenth International Conference on Architectural support for programming languages and operating systems10.1145/1736020.1736059(347-358)Online publication date: 13-Mar-2010
https://dl.acm.org/doi/10.1145/1736020.1736059
Gelado IStone JCabezas JPatel SNavarro NHwu W(2010)An asymmetric distributed shared memory model for heterogeneous parallel systemsACM SIGPLAN Notices10.1145/1735971.173605945:3(347-358)Online publication date: 13-Mar-2010
https://dl.acm.org/doi/10.1145/1735971.1736059
Gelado IStone JCabezas JPatel SNavarro NHwu W(2010)An asymmetric distributed shared memory model for heterogeneous parallel systemsACM SIGARCH Computer Architecture News10.1145/1735970.173605938:1(347-358)Online publication date: 13-Mar-2010
https://dl.acm.org/doi/10.1145/1735970.1736059
Show More Cited By

Index Terms

PLUS: a distributed shared-memory system
1. Hardware
  1. Hardware validation
  2. Integrated circuits
    1. Semiconductor memory

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Published In

cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 18, Issue 2SI

Special Issue: Proceedings of the 17th annual international symposium on Computer Architecture

June 1990

356 pages

ISSN:0163-5964

DOI:10.1145/325096

Issue’s Table of Contents

ISCA '90: Proceedings of the 17th annual international symposium on Computer Architecture
May 1990
378 pages
ISBN:0897913663
DOI:10.1145/325164
Chairmen:
Jean-Loup Baer,
Larry Snyder,
James Goodman

Copyright © 1990 Authors.

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 May 1990

Published in SIGARCH Volume 18, Issue 2SI

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Cited By

Gelado IStone JCabezas JPatel SNavarro NHwu WHoe JAdve V(2010)An asymmetric distributed shared memory model for heterogeneous parallel systemsProceedings of the fifteenth International Conference on Architectural support for programming languages and operating systems10.1145/1736020.1736059(347-358)Online publication date: 13-Mar-2010
https://dl.acm.org/doi/10.1145/1736020.1736059
Gelado IStone JCabezas JPatel SNavarro NHwu W(2010)An asymmetric distributed shared memory model for heterogeneous parallel systemsACM SIGPLAN Notices10.1145/1735971.173605945:3(347-358)Online publication date: 13-Mar-2010
https://dl.acm.org/doi/10.1145/1735971.1736059
Gelado IStone JCabezas JPatel SNavarro NHwu W(2010)An asymmetric distributed shared memory model for heterogeneous parallel systemsACM SIGARCH Computer Architecture News10.1145/1735970.173605938:1(347-358)Online publication date: 13-Mar-2010
https://dl.acm.org/doi/10.1145/1735970.1736059
Chaves EDas PLeblanc TMarsh BScott M(2006)Kernel‐Kernel communication in a shared‐memory multiprocessorConcurrency: Practice and Experience10.1002/cpe.43300503025:3(171-191)Online publication date: 24-Oct-2006
https://doi.org/10.1002/cpe.4330050302
Nash JDew PDavy JDyer M(2005)Implementation issues relating to the WPRAM model for scalable computingEuro-Par'96 Parallel Processing10.1007/BFb0024719(319-326)Online publication date: 10-Jun-2005
https://doi.org/10.1007/BFb0024719
Voliotis CManis GThanos ATsanakas PPapakonstantinou G(1995)Facilitating the development of portable parallel applications on distributed memory systemsProgramming Models for Massively Parallel Computers10.1109/PMMPC.1995.504356(176-183)Online publication date: 1995
https://doi.org/10.1109/PMMPC.1995.504356
(1995)ReferencesScalable Shared-Memory Multiprocessing10.1016/B978-1-55860-315-8.50017-8(317-331)Online publication date: 1995
https://doi.org/10.1016/B978-1-55860-315-8.50017-8
Su HYew PElliott R(1991)Efficient Doacross execution on distributed shared-memory multiprocessorsProceedings of the 1991 ACM/IEEE conference on Supercomputing10.1145/125826.105185(842-853)Online publication date: 1-Aug-1991
https://dl.acm.org/doi/10.1145/125826.105185
Shan YTsai SZhang Y(2017)Distributed shared persistent memoryProceedings of the 2017 Symposium on Cloud Computing10.1145/3127479.3128610(323-337)Online publication date: 24-Sep-2017
https://dl.acm.org/doi/10.1145/3127479.3128610
Nash JDew PDavy JDyer M(2005)Implementation issues relating to the WPRAM model for scalable computingEuro-Par'96 Parallel Processing10.1007/BFb0024719(319-326)Online publication date: 10-Jun-2005
https://doi.org/10.1007/BFb0024719
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