Article

A Compiler Directed Approach to Hiding Configuration Latency in Chameleon Processors

Authors:

Manning Aalsma,

Raymond JouAuthors Info & Claims

FPL '00: Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications

Pages 29 - 38

Published: 27 August 2000 Publication History

Abstract

The Chameleon CS2112 chip is the industry's first reconfigurable communication processor. To attain high performance, the reconfiguration latency must be effectively tolerated in such a processor. In this paper, we present a compiler directed approach to hiding the configuration loading latency. We integrate multithreading, instruction scheduling, register allocation, and prefetching techniques to tolerate the configuration loading latency. Furthermore, loading configuration is overlapped with communication to further enhance performance. By running some kernel programs on a cycle-accurate simulator, we showed that the chip performance is significantly improved by leveraging such compiler and multithreading techniques.

References

[1]

K. Bondalapati and V. K. Prasanna. "mapping loops onto reconfigurable architectures". In Proc. of Inter. Workshop on Field Programmable Logic and Applications, Sep. 1998.

[2]

M. Budiu and S. C. Goldstein. "fast compilation for pipelined reconfigurable fabric". In Proc. of ACM/SIGDA Inter. Symposium on FPGA, 1999.

[3]

T. J. Callahan and F. John Wawrzynek. "instruction level parallelism for reconfigurable computing". In Hartenstein and Keevallik, editors, Inter. Workshop on Field-Programmable Logic and Applications. Lecture Notes in Computer Science, LNCS 1482, Springer-Verlag, Aug. 1998.

[4]

Chameleon Systems, Inc. http://www.chameleonsystems.com/, 2000.

[5]

M. Gokhale and J. Stone. "NAPA C: Compiling for a hybrid risc/fpga architcture". In Proc. of the IEEE Symposium on FCCM, Apr. 1998.

[6]

S. C. Goldstein, H. Schmit, M. Moe, M. Budiu, S. Cadambi, R. R. Taylor, and R. Laufer. PipeRench: A coprocessor streaming multimedia acceleration. In Proc. of ISCA-26, pages 28-39, Atlanta, Geor., May 1999.

[7]

S. Hauck, T. W. Fry, M. M. Hosler, and J. P. Kao. "the chimaera reconfigurable functional unit". In Proc. of the IEEE Symposium on FCCM, Apr. 1997.

[8]

S. Hauck, T. W. Fry, M. M. Hosler, and J. P. Kao. "configuration prefetch for single context reconfigurable coprocessors". In Proc. of ACM/SIGDA Inter. Symposium on FPGA, Feb. 1998.

[9]

S. Hauck, Z. Li, and E. J. Schwabe. "configuration compression for the xilinx xc6200 fpga". In Proc. of the IEEE Symposium on FCCM, Apr. 1998.

[10]

J. R. Hauser and J. Wawrzynek. "garp: A mips processor with a reconfigurable coprocessor". In Proc. of the IEEE Symposium on FCCM, Apr. 1997.

[11]

S. S. Muchnick. Advanced Compiler Design and Implementation. Morgan Kaufmann Publishers, 1997.

[12]

R. Razdan. PRISC: Programmable Reduced Instruction Set Computers. PhD thesis, Harvard University, Division of Applied Sciences, Boston, 1994.

[13]

C. R. Rupp, M. Landguth, T. Garverick, E. Gomersall, H. Holt, J. M. Arnold, and M. Gokhale. "the napa adaptive processing architecture". In Proc. of the IEEE Symposium on FCCM, Apr. 1998.

[14]

S.K. Rajamani and P. Viswanath. "a quantitative analysis of the processor-programmable logic interface". In Proc. of the IEEE Symposium on FCCM, Apr. 1997.

[15]

X. Tang and G. R. Gao. Automatically partitioning threads for multithreaded architectures. Journal of Parallel and Distributed Computing, 58(2):159-189, Aug. 1999.

[16]

M. Weinhardt and W. Luk. "pipeline vectorization for reconfigurable systems". In Proc. of the IEEE Symposium on FCCM, Apr. 1999.

Cited By

Panainte EBertels KVassiliadis S(2006)Interprocedural Compiler Optimization for Partial Run-Time ReconfigurationJournal of VLSI Signal Processing Systems10.1007/s11265-006-7268-043:2-3(161-172)Online publication date: 1-Jun-2006
https://dl.acm.org/doi/10.1007/s11265-006-7268-0
Panainte EBertels KVassiliadis S(2005)Instruction Scheduling for Dynamic Hardware ConfigurationsProceedings of the conference on Design, Automation and Test in Europe - Volume 110.1109/DATE.2005.184(100-105)Online publication date: 7-Mar-2005
https://dl.acm.org/doi/10.1109/DATE.2005.184
Panainte EBertels KVassiliadis S(2005)Interprocedural optimization for dynamic hardware configurationsProceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation10.1007/11512622_2(2-11)Online publication date: 18-Jul-2005
https://dl.acm.org/doi/10.1007/11512622_2
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A Compiler Directed Approach to Hiding Configuration Latency in Chameleon Processors

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cover image Guide Proceedings

FPL '00: Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications

August 2000

852 pages

ISBN:3540678999

Publisher

Springer-Verlag

Berlin, Heidelberg

Publication History

Published: 27 August 2000

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Cited By

Panainte EBertels KVassiliadis S(2006)Interprocedural Compiler Optimization for Partial Run-Time ReconfigurationJournal of VLSI Signal Processing Systems10.1007/s11265-006-7268-043:2-3(161-172)Online publication date: 1-Jun-2006
https://dl.acm.org/doi/10.1007/s11265-006-7268-0
Panainte EBertels KVassiliadis S(2005)Instruction Scheduling for Dynamic Hardware ConfigurationsProceedings of the conference on Design, Automation and Test in Europe - Volume 110.1109/DATE.2005.184(100-105)Online publication date: 7-Mar-2005
https://dl.acm.org/doi/10.1109/DATE.2005.184
Panainte EBertels KVassiliadis S(2005)Interprocedural optimization for dynamic hardware configurationsProceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation10.1007/11512622_2(2-11)Online publication date: 18-Jul-2005
https://dl.acm.org/doi/10.1007/11512622_2
Heysters PSmit GMolenkamp E(2003)A Flexible and Energy-Efficient Coarse-Grained Reconfigurable Architecture for Mobile SystemsThe Journal of Supercomputing10.1023/A:102569901539826:3(283-308)Online publication date: 1-Nov-2003
https://dl.acm.org/doi/10.1023/A%3A1025699015398
David RChillet DPillement SSentieys O(2002)DARTProceedings of the 16th International Parallel and Distributed Processing Symposium10.5555/645610.663282Online publication date: 15-Apr-2002
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Lee SYoo SChoi KHenkel JHu XGupta RParameswaran S(2002)Reconfigurable SoC design with hierarchical FSM and synchronous dataflow modelProceedings of the tenth international symposium on Hardware/software codesign10.1145/774789.774830(199-204)Online publication date: 6-May-2002
https://dl.acm.org/doi/10.1145/774789.774830
Baleani MGennari FJiang YPatel YBrayton RSangiovanni-Vincentelli AHenkel JHu XGupta RParameswaran S(2002)HW/SW partitioning and code generation of embedded control applications on a reconfigurable architecture platformProceedings of the tenth international symposium on Hardware/software codesign10.1145/774789.774820(151-156)Online publication date: 6-May-2002
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Hartenstein R(2001)A decade of reconfigurable computingProceedings of the conference on Design, automation and test in Europe10.5555/367072.367839(642-649)Online publication date: 13-Mar-2001
https://dl.acm.org/doi/10.5555/367072.367839
Schaumont PVerbauwhede IKeutzer KSarrafzadeh MRabaey J(2001)A quick safari through the reconfiguration jungleProceedings of the 38th annual Design Automation Conference10.1145/378239.378404(172-177)Online publication date: 22-Jun-2001
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Hartenstein RGoto S(2001)Coarse grain reconfigurable architecture (embedded tutorial)Proceedings of the 2001 Asia and South Pacific Design Automation Conference10.1145/370155.370535(564-570)Online publication date: 30-Jan-2001
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