Article

Reducing power requirements of instruction scheduling through dynamic allocation of multiple datapath resources

Authors:

Dmitry Ponomarev,

Kanad GhoseAuthors Info & Claims

MICRO 34: Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture

Pages 90 - 101

Published: 01 December 2001 Publication History

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Abstract

The "one-size-fits-all" philosophy used for permanently allocating datapath resources in today's superscalar CPUs to maximize performance across a wide range of applications results in the overcommitment of resources in general. To reduce power dissipation in the datapath, the resource allocations can be dynamically adjusted based on the demands of applications. We propose a mechanism to dynamically, simultaneously and independently adjust the sizes of the issue queue (IQ), the reorder buffer (ROB) and the load/store queue (LSQ) based on the periodic sampling of their occupancies to achieve significant power savings with minimal impact on performance. Resource upsizing is done more aggressively (compared to downsizing) using the relative rate of blocked dispatches to limit the performance penalty. Our results are validated by the execution of SPEC 95 benchmark suite on a substantially modified version of Simplescalar simulator, where the IQ, the ROB, the LSQ and the register files are implemented as separate structures, as is the case with most practical implementations. For the SPEC 95 benchmarks, the use of our technique in a 4-way superscalar processor results in a power savings in excess of 70% within individual components and an average power savings of 53% for the IQ, LSQ and ROB combined for the entire benchmark suite with an average performance penalty of only 5%.

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Reducing power requirements of instruction scheduling through dynamic allocation of multiple datapath resources
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Published In

cover image ACM Conferences

MICRO 34: Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture

December 2001

355 pages

ISBN:0769513697

General Chair:
Yale Patt
The University of Texas at Austin
,
Program Chairs:
Josh Fisher
Hewlett-Packard Laboratories
,
Paolo Faraboschi
Hewlett-Packard Laboratories
,
Publications Chair:
Kevin Skadron
University of Virginia

Copyright © Copyright (c) 2001 Institute of Electrical and Electronics Engineers, Inc. All rights reserved.

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IEEE Computer Society

United States

Publication History

Published: 01 December 2001

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MICRO-34

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SIGMICRO

MICRO-34: The 34th International Symposium on Microarchitecture

December 1 - 5, 2001

Texas, Austin

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Overall Acceptance Rate 484 of 2,242 submissions, 22%

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https://dl.acm.org/doi/10.5555/3489146.3489170
Ding YMishra NHoffmann HManne SHunter HAltman E(2019)Generative and multi-phase learning for computer systems optimizationProceedings of the 46th International Symposium on Computer Architecture10.1145/3307650.3326633(39-52)Online publication date: 22-Jun-2019
https://dl.acm.org/doi/10.1145/3307650.3326633
Mishra NImes CLafferty JHoffmann H(2018)CALOREEACM SIGPLAN Notices10.1145/3296957.317318453:2(184-198)Online publication date: 19-Mar-2018
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