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Data flow on a queue machine

Authors:

Bruno R. Preiss,

V. C. HamacherAuthors Info & Claims

ISCA '85: Proceedings of the 12th annual international symposium on Computer architecture

Pages 342 - 351

Published: 01 June 1985 Publication History

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References

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Cited By

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Fernandes SOliveira BSilva ISaraiva IRibas RPlett C(2009)Using NoC routers as processing elementsProceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes10.1145/1601896.1601927(1-6)Online publication date: 31-Aug-2009
https://dl.acm.org/doi/10.1145/1601896.1601927
Canedo AAbderazek BSowa M(2009)Efficient compilation for queue size constrained queue processorsParallel Computing10.1016/j.parco.2008.11.00435:4(213-225)Online publication date: 1-Apr-2009
https://dl.acm.org/doi/10.1016/j.parco.2008.11.004
Canedo AAbderazek BSowa M(2009)Design and implementation of a queue compilerMicroprocessors & Microsystems10.1016/j.micpro.2008.09.00133:2(129-138)Online publication date: 1-Mar-2009
https://dl.acm.org/doi/10.1016/j.micpro.2008.09.001
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Data flow on a queue machine

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Information & Contributors

Information

Published In

ISCA '85: Proceedings of the 12th annual international symposium on Computer architecture

June 1985

428 pages

ISBN:0818606347

Chairmen:
Thomas Gannon
Digital Equipment Corp.
,
Tilak Agerwala
IBM Research
,
Charles Freiman
IBM Research

ACM SIGARCH Computer Architecture News Volume 13, Issue 3
Special Issue: Proceedings of the 12th annual international symposium on Computer architecture (ISCA '85)
June 1985
396 pages
ISSN:0163-5964
DOI:10.1145/327070
Chairmen:
Thomas Gannon
Digital Equipment Corp.
,
Tilak Agerwala
IBM Research
,
Charles Freiman
IBM Research
Issue’s Table of Contents

Publisher

IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 01 June 1985

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Conference

ISCA85

Sponsor:

SIGARCH

ISCA85: International Symposium on Computer Architecture

June 17 - 19, 1985

Massachusetts, Boston, USA

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Overall Acceptance Rate 543 of 3,203 submissions, 17%

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ISCA '25

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The 52nd Annual International Symposium on Computer Architecture

June 21 - 25, 2025

Tokyo , Japan

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Cited By

View all

Fernandes SOliveira BSilva ISaraiva IRibas RPlett C(2009)Using NoC routers as processing elementsProceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes10.1145/1601896.1601927(1-6)Online publication date: 31-Aug-2009
https://dl.acm.org/doi/10.1145/1601896.1601927
Canedo AAbderazek BSowa M(2009)Efficient compilation for queue size constrained queue processorsParallel Computing10.1016/j.parco.2008.11.00435:4(213-225)Online publication date: 1-Apr-2009
https://dl.acm.org/doi/10.1016/j.parco.2008.11.004
Canedo AAbderazek BSowa M(2009)Design and implementation of a queue compilerMicroprocessors & Microsystems10.1016/j.micpro.2008.09.00133:2(129-138)Online publication date: 1-Mar-2009
https://dl.acm.org/doi/10.1016/j.micpro.2008.09.001
Canedo AAbderazek BSowa M(2007)An efficient code generation algorithm for code size reduction using 1-offset P-code queue computation modelProceedings of the 2007 international conference on Embedded and ubiquitous computing10.5555/1780745.1780768(196-208)Online publication date: 17-Dec-2007
https://dl.acm.org/doi/10.5555/1780745.1780768
Sowa MAbderazek BYoshinaga T(2005)Parallel Queue Processor Architecture Based on Produced Order Computation ModelThe Journal of Supercomputing10.1007/s11227-005-0160-z32:3(217-229)Online publication date: 1-Jun-2005
https://dl.acm.org/doi/10.1007/s11227-005-0160-z
Abderazek BShigeta SYoshinaga TSowa M(2003)On the design of a register queue based processor architecture (FaRM-rq)Proceedings of the 2003 international conference on Parallel and distributed processing and applications10.5555/1761566.1761600(248-262)Online publication date: 2-Jul-2003
https://dl.acm.org/doi/10.5555/1761566.1761600
Dai KGiloi WSameh Avan der Vorst H(1990)A basic architecture supporting LGDG computationProceedings of the 4th international conference on Supercomputing10.1145/77726.255135(23-33)Online publication date: 1-Jun-1990
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Dai KGiloi W(1990)A basic architecture supporting LGDG computationACM SIGARCH Computer Architecture News10.1145/255129.25513518:3b(23-33)Online publication date: 1-Jun-1990
https://dl.acm.org/doi/10.1145/255129.255135
Ben Abdallah ABen Abdallah A(2017)Parallelizing Compiler for Single and Multicore ComputingAdvanced Multicore Systems-On-Chip10.1007/978-981-10-6092-2_7(201-223)Online publication date: 12-Sep-2017
https://doi.org/10.1007/978-981-10-6092-2_7
Abderazek BMasuda MCanedo AKuroda K(2011)Natural instruction level parallelism-aware compiler for high-performance QueueCore processor architectureThe Journal of Supercomputing10.1007/s11227-010-0409-z57:3(314-338)Online publication date: 1-Sep-2011
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The cyclic queue and the tandem queue

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