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An evolutionary approach to hardware encryption and trojan-horse mitigation

Published: 27 March 2017 Publication History

Abstract

New threats, grouped under the name of hardware attacks, became a serious concern in recent years. In a global market, untrusted parties in the supply chain may jeopardize the production of integrated circuits with intellectual-property piracy, illegal overproduction and hardware Trojan-horses (HT) injection. While one way to protect from overproduction is to encrypt the design by inserting logic gates that prevents the circuit from generating the correct outputs unless the right key is used, reducing the number of poorly-controllable signals is known to minimize the chances for an attacker to successfully hide the trigger for some malicious payload. Several approaches successfully tackled independently these two issues. This paper proposes a novel technique based on a multi-objective evolutionary algorithm able to increase hardware security by explicitly targeting both the minimization of rare signals and the maximization of the efficacy of logic encryption. Experimental results demonstrate the proposed method is effective in creating a secure encryption schema for all the circuits under test and in reducing the number rare signals on six circuits over nine, outperforming the current state of the art.

References

[1]
J. A. Roy, F. Koushanfar, and I. L. Markov, "Epic: Ending piracy of integrated circuits," in Proceedings of the conference on Design, automation and test in Europe. ACM, 2008, pp. 1069--1074.
[2]
J. Rajendran, Y. Pino, O. Sinanoglu, and R. Karri, "Logic encryption: A fault analysis perspective," in Proceedings of the Conference on Design, Automation and Test in Europe. EDA Consortium, 2012, pp. 953--958.
[3]
X. Wang, M. Tehranipoor, and J. Plusquellic, "Detecting malicious inclusions in secure hardware: Challenges and solutions," in Hardware-Oriented Security and Trust, 2008. HOST 2008. IEEE International Workshop on. IEEE, 2008, pp. 15--19.
[4]
M. Tehranipoor and F. Koushanfar, "A survey of hardware trojan taxonomy and detection," IEEE Design and Test of Computers, vol. 27, no. 1, pp. 10--25, 2010.
[5]
S. Dupuis, G. Di Natale, M.-L. Flottes, and B. Rouzeyre, "Identification of hardware trojans triggering signals," in First Workshop on Trustworthy Manufacturing and Utilization of Secure Devices, 2013.
[6]
R. S. Chakraborty and S. Bhunia, "Security against hardware trojan through a novel application of design obfuscation," in Proceedings of the 2009 International Conference on Computer-Aided Design. ACM, 2009, pp. 113--116.
[7]
H. Salmani, M. Tehranipoor, and J. Plusquellic, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 20, no. 1, pp. 112--125, 2012.
[8]
S. Dupuis, P.-S. Ba, G. Di Natale, M.-L. Flottes, and B. Rouzeyre, "A novel hardware logic encryption technique for thwarting illegal overproduction and hardware trojans," in 2014 IEEE 20th International On-Line Testing Symposium (IOLTS). IEEE, 2014, pp. 49--54.
[9]
J. Rajendran, H. Zhang, C. Zhang, G. S. Rose, Y. Pino, O. Sinanoglu, and R. Karri, "Fault analysis-based logic encryption," IEEE Transactions on Computers, vol. 64, no. 2, pp. 410--424, 2015.
[10]
M. S. Samimi, E. Aerabi, Z. Kazemi, M. Fazeli, and A. Patooghy, "Hardware enlightening: No where to hide your hardware trojans!" in On-Line Testing and Robust System Design (IOLTS), 2016 IEEE 22nd International Symposium on. IEEE, 2016, pp. 251--256.
[11]
K. Deb, "Multi-objective optimization," in Search methodologies. Springer, 2014, pp. 403--449.
[12]
A. E. Eiben and J. E. Smith, Introduction to evolutionary computing (2nd edition). Springer, 2015, vol. 53.
[13]
E. Sanchez, M. Schillaci, and G. Squillero, Evolutionary Optimization: the μGP toolkit. Springer Science & Business Media, 2011.
[14]
K. Deb, A. Pratap, S. Agarwal, and T. Meyarivan, "A fast and elitist multiobjective genetic algorithm: Nsga-ii," IEEE transactions on evolutionary computation, vol. 6, no. 2, pp. 182--197, 2002.

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cover image Guide Proceedings
DATE '17: Proceedings of the Conference on Design, Automation & Test in Europe
March 2017
1814 pages

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European Design and Automation Association

Leuven, Belgium

Publication History

Published: 27 March 2017

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