This article presents a technique for the extension of delay fault test pattern generation to synchronous sequential circuits without making use of scan techniques. The technique relies on the coupling of TDgen, a robust combinational test pattern ...
The path delay fault testability of sequential circuits is limited by state transitions that can be produced during normal operation. As a result, there may be untestable faults some of which may affect circuit behavior. The authors first extend the ...
A method to design and test asynchronous sequential circuits (ASCs) based on the micropipeline design style is presented in this paper. According to the proposed scan test approach the combinational block is tested separately by scanning the test ...
IEEE Computer Society Press
Washington, DC, United States
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