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Reducing CTL-live Model Checking to First-Order Logic Validity Checking

Authors:

Amirhossein Vakili,

Nancy A. DayAuthors Info & Claims

FMCAD '14: Proceedings of the 14th Conference on Formal Methods in Computer-Aided Design

Pages 215 - 218

Published: 21 October 2014 Publication History

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Abstract

Temporal logic model checking of infinite state systems without the use of iteration or abstraction is usually considered beyond the realm of first-order logic (FOL) reasoners because of the need for a fixpoint computation. In this paper, we show that it is possible to reduce model checking of a finite or infinite Kripke structure that is expressed in FOL to a validity problem in FOL for a fragment of computational tree logic (CTL), which we call CTL-live. CTL-live includes the CTL connectives that are traditionally used to express liveness properties. Our reduction can form the basis for methods that use FOL reasoning techniques directly to accomplish model checking of CTL-live properties without the need for fixpoint operators, transitive closure, abstraction, or induction.

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Cited By

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Day NVakili A(2016)Representing hierarchical state machine models in SMT-LIBProceedings of the 8th International Workshop on Modeling in Software Engineering10.1145/2896982.2896990(67-73)Online publication date: 14-May-2016
https://dl.acm.org/doi/10.1145/2896982.2896990
Vakili ADay NCheung SOrso AStorey M(2014)Verifying CTL-live properties of infinite state models using an SMT solverProceedings of the 22nd ACM SIGSOFT International Symposium on Foundations of Software Engineering10.1145/2635868.2635911(213-223)Online publication date: 11-Nov-2014
https://dl.acm.org/doi/10.1145/2635868.2635911

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Reducing CTL-live Model Checking to First-Order Logic Validity Checking

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Published In

FMCAD '14: Proceedings of the 14th Conference on Formal Methods in Computer-Aided Design

October 2014

219 pages

ISBN:9780983567844

Editors:
Koen Claessen,
Viktor Kuncak,
Publications Chair:
Barbara Jobstmann

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FMCAD Inc

Austin, Texas

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Published: 21 October 2014

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FMCAD '14: Formal Methods in Computer-Aided Design

October 21 - 24, 2014

Lausanne, Switzerland

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Cited By

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Day NVakili A(2016)Representing hierarchical state machine models in SMT-LIBProceedings of the 8th International Workshop on Modeling in Software Engineering10.1145/2896982.2896990(67-73)Online publication date: 14-May-2016
https://dl.acm.org/doi/10.1145/2896982.2896990
Vakili ADay NCheung SOrso AStorey M(2014)Verifying CTL-live properties of infinite state models using an SMT solverProceedings of the 22nd ACM SIGSOFT International Symposium on Foundations of Software Engineering10.1145/2635868.2635911(213-223)Online publication date: 11-Nov-2014
https://dl.acm.org/doi/10.1145/2635868.2635911

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Reduction from branching-time property verification of higher-order programs to HFL validity checking

Model checking for a first-order temporal logic using multiway decision graphs