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The design and performance of a conflict-avoiding cache

Authors:

Antonio González,

José GonzálezAuthors Info & Claims

MICRO 30: Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture

Pages 71 - 80

Published: 01 December 1997 Publication History

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Abstract

High performance architectures depend heavily on efficient multi-level memory hierarchies to minimize the cost of accessing data. This dependence will increase with the expected increases in relative distance to main memory. There have been a number of published proposals for cache conflict-avoidance schemes. We investigate the design and performance of conflict-avoiding cache architectures based on polynomial modulus functions, which earlier research has shown to be highly effective at reducing conflict miss ratios. We examine a number of practical implementation issues and present experimental evidence to support the claim that pseudo-randomly indexed caches are both effective in performance terms and practical from an implementation viewpoint.

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Cited By

Wang BLiu ZWang XYu WNebel WAtienza D(2015)Eliminating intra-warp conflict misses in GPUProceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition10.5555/2755753.2755911(689-694)Online publication date: 9-Mar-2015
https://dl.acm.org/doi/10.5555/2755753.2755911
Khairy MZahran MWassal AKaeli DCavazos J(2015)Efficient utilization of GPGPU cache hierarchyProceedings of the 8th Workshop on General Purpose Processing using GPUs10.1145/2716282.2716291(36-47)Online publication date: 7-Feb-2015
https://dl.acm.org/doi/10.1145/2716282.2716291
Chaturvedi NGurunarayanan S(2015)An efficient adaptive block pinning for multicore architecturesMicroprocessors & Microsystems10.1016/j.micpro.2015.02.00639:3(181-188)Online publication date: 1-May-2015
https://dl.acm.org/doi/10.1016/j.micpro.2015.02.006
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The design and performance of a conflict-avoiding cache

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Published In

cover image ACM Conferences

MICRO 30: Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture

December 1997

369 pages

ISBN:0818679778

Chairmen:
Mark Smotherman
Clemson Univ., Clemson, SC
,
Tom Conte
North Carolina State Univ., Raleigh

Copyright © Copyright (c) 1997 Institute of Electrical and Electronics Engineers, Inc. All rights reserved.

Sponsors

SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing
IEEE-CS\TCMM: TC on Microprocessors & Microcomputers

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IEEE Computer Society

United States

Publication History

Published: 01 December 1997

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MICRO97

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SIGMICRO
IEEE-CS\TCMM

MICRO97: 30th Annual International Symposium on Microarchitecture

December 1 - 3, 1997

North Carolina, Research Triangle Park, USA

Acceptance Rates

MICRO 30 Paper Acceptance Rate 35 of 103 submissions, 34%;

Overall Acceptance Rate 484 of 2,242 submissions, 22%

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MICRO '24

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sigmicro

57th Annual IEEE/ACM International Symposium on Microarchitecture

November 2 - 6, 2024

Austin , TX , USA

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Cited By

Wang BLiu ZWang XYu WNebel WAtienza D(2015)Eliminating intra-warp conflict misses in GPUProceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition10.5555/2755753.2755911(689-694)Online publication date: 9-Mar-2015
https://dl.acm.org/doi/10.5555/2755753.2755911
Khairy MZahran MWassal AKaeli DCavazos J(2015)Efficient utilization of GPGPU cache hierarchyProceedings of the 8th Workshop on General Purpose Processing using GPUs10.1145/2716282.2716291(36-47)Online publication date: 7-Feb-2015
https://dl.acm.org/doi/10.1145/2716282.2716291
Chaturvedi NGurunarayanan S(2015)An efficient adaptive block pinning for multicore architecturesMicroprocessors & Microsystems10.1016/j.micpro.2015.02.00639:3(181-188)Online publication date: 1-May-2015
https://dl.acm.org/doi/10.1016/j.micpro.2015.02.006
Govindan SLiu JKansal ASivasubramaniam AChase JAbbadi A(2011)CuantaProceedings of the 2nd ACM Symposium on Cloud Computing10.1145/2038916.2038938(1-14)Online publication date: 26-Oct-2011
https://dl.acm.org/doi/10.1145/2038916.2038938
Hammoud MCho SMelhem RKatevenis MMartonosi MKozyrakis CTemam O(2011)Cache equalizerProceedings of the 6th International Conference on High Performance and Embedded Architectures and Compilers10.1145/1944862.1944889(177-186)Online publication date: 24-Jan-2011
https://dl.acm.org/doi/10.1145/1944862.1944889
Song FLiu ZFan DZhang HYu LTang S(2010)Thread owned block cacheProceedings of the 16th international Euro-Par conference on Parallel processing: Part I10.5555/1887695.1887727(292-303)Online publication date: 31-Aug-2010
https://dl.acm.org/doi/10.5555/1887695.1887727
Vandierendonck HDe Bosschere K(2008)Constructing optimal XOR-functions to minimize cache conflict missesProceedings of the 21st international conference on Architecture of computing systems10.5555/1787770.1787798(261-272)Online publication date: 25-Feb-2008
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Srikantaiah SKandemir MIrwin M(2008)Adaptive set pinningACM SIGPLAN Notices10.1145/1353536.134629943:3(135-144)Online publication date: 1-Mar-2008
https://dl.acm.org/doi/10.1145/1353536.1346299
Srikantaiah SKandemir MIrwin M(2008)Adaptive set pinningACM SIGOPS Operating Systems Review10.1145/1353535.134629942:2(135-144)Online publication date: 1-Mar-2008
https://dl.acm.org/doi/10.1145/1353535.1346299
Srikantaiah SKandemir MIrwin M(2008)Adaptive set pinningACM SIGARCH Computer Architecture News10.1145/1353534.134629936:1(135-144)Online publication date: 1-Mar-2008
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