research-article

Width minimization in the single-electron transistor array synthesis

Authors:

Chang-En Chiang,

Ching-Yi Huang,

Yung-Chih Chen,

Vijaykrishnan NarayananAuthors Info & Claims

DATE '14: Proceedings of the conference on Design, Automation & Test in Europe

Article No.: 122, Pages 1 - 4

Published: 24 March 2014 Publication History

Abstract

Power consumption has become one of the primary challenges to meet the Moore's law. For reducing power consumption, Single-Electron Transistor (SET) at room temperature has been demonstrated as a promising device for extending Moore's law due to its ultra-low power consumption during operation. Prior work has proposed an automated mapping approach for SET arrays which focuses on minimizing the number of hexagons in an SET array. However, the area of an SET array is more related to the width. Consequently, in this work, we propose an approach for width minimization of the SET arrays. The experimental results show that the proposed approach saves 26% of width compared with the state-of-the-art for a set of MCNC and IWLS 2005 benchmarks while spending similar CPU time.

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Cited By

Li YHuang CWu CChen YWang CDatta SNarayanan V(2017)Dynamic Diagnosis for Defective Reconfigurable Single-Electron Transistor ArraysIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.263953325:4(1477-1489)Online publication date: 1-Apr-2017
https://dl.acm.org/doi/10.1109/TVLSI.2016.2639533
Chen YChen JHuang J(2016)Area Minimization Synthesis for Reconfigurable Single-Electron Transistor Arrays with Fabrication ConstraintsACM Journal on Emerging Technologies in Computing Systems10.1145/290636012:4(1-15)Online publication date: 13-May-2016
https://dl.acm.org/doi/10.1145/2906360
Ho CChen YWang CHuang CDatta SNarayanan V(2016)Area-Aware Decomposition for Single-Electron Transistor ArraysACM Transactions on Design Automation of Electronic Systems10.1145/289899821:4(1-20)Online publication date: 14-Sep-2016
https://dl.acm.org/doi/10.1145/2898998

Index Terms

Width minimization in the single-electron transistor array synthesis
1. Applied computing
  1. Physical sciences and engineering
    1. Electronics
2. Hardware
  1. Integrated circuits
  2. Robustness

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DATE '14: Proceedings of the conference on Design, Automation & Test in Europe

As fabrication processes exploit even deeper submicron technology, power dissipation has become a crucial issue for most electronic circuit and system designs nowadays. In particular, leakage power is becoming a dominant source of power consumption. ...

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Information

Published In

cover image ACM Other conferences

DATE '14: Proceedings of the conference on Design, Automation & Test in Europe

March 2014

1959 pages

ISBN:9783981537024

General Chairs:
Gerhard Fettweis
TU Dresden, DE
,
Wolfgang Nebel
OFFIS, DE

Sponsors

EDAA: European Design Automation Association
ECSI
EDAC: Electronic Design Automation Consortium
IEEE Council on Electronic Design Automation (CEDA)
The Russian Academy of Sciences: The Russian Academy of Sciences

In-Cooperation

SIGDA: ACM Special Interest Group on Design Automation

Publisher

European Design and Automation Association

Leuven, Belgium

Publication History

Published: 24 March 2014

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DATE '14

Sponsor:

EDAA
EDAC
The Russian Academy of Sciences

DATE '14: Design, Automation and Test in Europe

March 24 - 28, 2014

Dresden, Germany

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Overall Acceptance Rate 518 of 1,794 submissions, 29%

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Cited By

Li YHuang CWu CChen YWang CDatta SNarayanan V(2017)Dynamic Diagnosis for Defective Reconfigurable Single-Electron Transistor ArraysIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.263953325:4(1477-1489)Online publication date: 1-Apr-2017
https://dl.acm.org/doi/10.1109/TVLSI.2016.2639533
Chen YChen JHuang J(2016)Area Minimization Synthesis for Reconfigurable Single-Electron Transistor Arrays with Fabrication ConstraintsACM Journal on Emerging Technologies in Computing Systems10.1145/290636012:4(1-15)Online publication date: 13-May-2016
https://dl.acm.org/doi/10.1145/2906360
Ho CChen YWang CHuang CDatta SNarayanan V(2016)Area-Aware Decomposition for Single-Electron Transistor ArraysACM Transactions on Design Automation of Electronic Systems10.1145/289899821:4(1-20)Online publication date: 14-Sep-2016
https://dl.acm.org/doi/10.1145/2898998

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