skip to main content
10.5555/1129601.1129660acmconferencesArticle/Chapter ViewAbstractPublication PagesiccadConference Proceedingsconference-collections
Article

Noise margin analysis for dynamic logic circuits

Published: 31 May 2005 Publication History

Abstract

We consider the problem of noise margin analysis for dynamic logic circuits. Because such circuits operate in multiple phases, their noise immunity is also time varying. We formulate noise margin analysis as a non-linear optimization problem where we find the smallest disturbance waveform that results in a qualitative change in the behavior of the circuit. We present a practical method for solving these optimization problems based on deriving a sensitivity matrix for the small-signal response of the circuit. We use our approach to compare the robustness of static CMOS gates, self-resetting domino, and output prediction logic.

References

[1]
{CC+91} T. I. Chappell, B. A. Chappell, et al. A 2-ns cycle, 3.8-ns access 512-kb CMOS ECL SRAM with a fully pipelined architecture. IEEE J. of Solid-State Circuits, 26(11):1577-1585, November 1991.
[2]
{GN04} T. Gemmeke and T. G. Noll. A physically oriented model to quantify the dynamic noise margin. In Proc. 30th Eur. Conf. on Solid-State Circuits, pp. 467-470, Sept. 2004.
[3]
{LS94} P. Larsson and C. Svensson. Noise in digital dynamic cmos circuits. IEEE J. of Solid-State Circuits, 29(6):655-662, Jun. 1994.
[4]
{MK+00} L. McMurchie, S. Kio, et al. Output prediction logic: A high-performance CMOS design technique. In Proc. of the 2000 Int'l. Conf. on Computer Design, pp. 247-254, 2000.
[5]
{SC00} K.L. Shepard and K. Chou. Cell characterization for noise stability. IEEE 2000 Custom Integrated Circuits Conf., pp. 91-94, 2000.
[6]
{SN96} K.L. Shepard and V. Narayanan. Noise in deep submicron digital design. In Proc. 1996 Int'l. Conf. on Computer Aided Design, pp. 406-411, 1996.
[7]
{ZB+02} V. Zolotov, D. Blaauw, et al. Noise propagation and failure criteria for vlsi designs. In IEEE/ACM Int'l. Conf. on Computer Aided Design, pp. 587-594, Nov. 2002.

Cited By

View all
  1. Noise margin analysis for dynamic logic circuits

    Recommendations

    Comments

    Information & Contributors

    Information

    Published In

    cover image ACM Conferences
    ICCAD '05: Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
    May 2005
    1032 pages
    ISBN:078039254X

    Sponsors

    Publisher

    IEEE Computer Society

    United States

    Publication History

    Published: 31 May 2005

    Check for updates

    Qualifiers

    • Article

    Acceptance Rates

    Overall Acceptance Rate 457 of 1,762 submissions, 26%

    Contributors

    Other Metrics

    Bibliometrics & Citations

    Bibliometrics

    Article Metrics

    • Downloads (Last 12 months)0
    • Downloads (Last 6 weeks)0
    Reflects downloads up to 06 Jan 2025

    Other Metrics

    Citations

    Cited By

    View all

    View Options

    Login options

    View options

    PDF

    View or Download as a PDF file.

    PDF

    eReader

    View online with eReader.

    eReader

    Media

    Figures

    Other

    Tables

    Share

    Share

    Share this Publication link

    Share on social media