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Coarse-Grain Coherence Tracking: RegionScout and Region Coherence Arrays

Published: 01 January 2006 Publication History

Abstract

Coarse-grain coherence tracking is a new technique that extends a conventional coherence mechanism and optimizes coherence enforcement. It monitors the coherence status of large regions of memory and uses that information to avoid unnecessary broadcasts and filter unnecessary cache tag lookups, thus improving system performance and power consumption.

References

[1]
A. Charlesworth, "The Sun Fireplane System Interconnect," Proc. Conf. Supercomputing (SC 01), ACM Press, 2001, p. 7.
[2]
J. Tendler, S. Dodson, and S. Fields, IBM eServer Power4 System Microarchitecture, tech. white paper, IBM Server Group, 2001.
[3]
A. Moshovos et al., "JETTY: Filtering Snoops for Reduced Energy Consumption in SMP Servers," Proc. 7th Int'l Symp. High Performance Computer Architecture (HPCA 01), IEEE Press, 2001, pp. 85-96.
[4]
A. Moshovos, "RegionScout: Exploiting Coarse Grain Sharing in Snoop-Based Coherence," Proc. Int'l Symp. Computer Architecture (ISCA 05), ACM Press, 2005, pp. 234-245.
[5]
J. Cantin, M. Lipasti, and J. Smith, "Improving Multiprocessor Performance with Coarse-Grain Coherence Tracking," Proc. Int'l Symp. Computer Architecture (ISCA 05), ACM Press, 2005, pp. 246-257.
[6]
H. Cain et al., "Precise and Accurate Processor Simulation," Proc. Workshop Computer Architecture Evaluation Using Commercial Workloads, 2002,
[7]
Y. Chou, L. Spracklen, and S. G. Abraham, "Store Memory-Level Parallelism Optimizations for Commercial Applications," Proc. 38th Ann. IEEE/ACM Int'l Symp. Microarchitecture (Micro-38), IEEE Press, 2005, pp. 183-196.
[8]
A. Moshovos et al., "JETTY: Filtering Snoops for Reduced Energy Consumption in SMP Servers," Proc. 7th Int'l Symp. High Performance Computer Architecture (HPCA 01), IEEE Press, 2001, pp. 85-96.
[9]
M. Ekman, F. Dahlgren, and P. Stenström, "TLB and Snoop Energy-Reduction Using Virtual Caches in Low-Power Chip-Multiprocessors," Proc. Int'l Symp. Low Power Electronics and Design (ISLPED 02), ACM Press, 2002, pp. 243-246.
[10]
C. May et al. (eds.) The PowerPC Architecture: A Specification for a New Family of RISC Processors (2nd ed.), Morgan Kaufmann, 1994.

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Published In

cover image IEEE Micro
IEEE Micro  Volume 26, Issue 1
January 2006
136 pages

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IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 01 January 2006

Author Tags

  1. RegionScout
  2. cache tag lookups
  3. coarse-grain coherence tracking
  4. power consumption
  5. region coherence arrays

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