article

A highly configurable cache architecture for embedded systems

Authors:

Chuanjun Zhang,

Walid NajjarAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 31, Issue 2

Pages 136 - 146

https://doi.org/10.1145/871656.859635

Published: 01 May 2003 Publication History

Abstract

Energy consumption is a major concern in many embedded computing systems. Several studies have shown that cache memories account for about 50% of the total energy consumed in these systems. The performance of a given cache architecture is largely determined by the behavior of the application using that cache. Desktop systems have to accommodate a very wide range of applications and therefore the manufacturer usually sets the cache architecture as a compromise given current applications, technology and cost. Unlike desktop systems, embedded systems are designed to run a small range of well-defined applications. In this context, a cache architecture that is tuned for that narrow range of applications can have both increased performance as well as lower energy consumption. We introduce a novel cache architecture intended for embedded microprocessor platforms. The cache can be configured by software to be direct-mapped, two-way, or four-way set associative, using a technique we call way concatenation, having very little size or performance overhead. We show that the proposed cache architecture reduces energy caused by dynamic power compared to a way-shutdown cache. Furthermore, we extend the cache architecture to also support a way shutdown method designed to reduce the energy from static power that is increasing in importance in newer CMOS technologies. Our study of 23 programs drawn from Powerstone, MediaBench and Spec2000 show that tuning the cache's configuration saves energy for every program compared to conventional four-way set-associative as well as direct mapped caches, with average savings of 40% compared to a four-way conventional cache.

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Cited By

Sun BKloda TGarcia SGracioli GCaccamo M(2024)Minimizing cache usage with fixed-priority and earliest deadline first schedulingReal-Time Systems10.1007/s11241-024-09423-7Online publication date: 28-Jun-2024
https://doi.org/10.1007/s11241-024-09423-7
Vazquez REdun AGordon-Ross AStitt G(2021)Dynamic Scheduling for Heterogeneous MulticoresSN Computer Science10.1007/s42979-021-00909-w2:6Online publication date: 18-Oct-2021
https://doi.org/10.1007/s42979-021-00909-w
Bandara SKinsy M(2020)Adaptive caches as a defense mechanism against cache side-channel attacksJournal of Cryptographic Engineering10.1007/s13389-020-00246-311:3(239-255)Online publication date: 28-Oct-2020
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A highly configurable cache architecture for embedded systems
1. Hardware
  1. Integrated circuits
    1. Semiconductor memory

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Information

Published In

cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 31, Issue 2

ISCA 2003

May 2003

422 pages

ISSN:0163-5964

DOI:10.1145/871656

Issue’s Table of Contents

ISCA '03: Proceedings of the 30th annual international symposium on Computer architecture
June 2003
432 pages
ISBN:0769519458
DOI:10.1145/859618
Conference Chair:
Allan Gottlieb
New York University & NEC Laboratories America
,
Program Chair:
Kai Li
Princeton University

Copyright © 2003 Authors.

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 May 2003

Published in SIGARCH Volume 31, Issue 2

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Cited By

Sun BKloda TGarcia SGracioli GCaccamo M(2024)Minimizing cache usage with fixed-priority and earliest deadline first schedulingReal-Time Systems10.1007/s11241-024-09423-7Online publication date: 28-Jun-2024
https://doi.org/10.1007/s11241-024-09423-7
Vazquez REdun AGordon-Ross AStitt G(2021)Dynamic Scheduling for Heterogeneous MulticoresSN Computer Science10.1007/s42979-021-00909-w2:6Online publication date: 18-Oct-2021
https://doi.org/10.1007/s42979-021-00909-w
Bandara SKinsy M(2020)Adaptive caches as a defense mechanism against cache side-channel attacksJournal of Cryptographic Engineering10.1007/s13389-020-00246-311:3(239-255)Online publication date: 28-Oct-2020
https://doi.org/10.1007/s13389-020-00246-3
Yasir Qadri MQadri NFleury MMcDonald-Maier K(2017)Energy-efficient data prefetch buffering for low-end embedded processorsMicroelectronics Journal10.1016/j.mejo.2017.01.01462(57-64)Online publication date: Apr-2017
https://doi.org/10.1016/j.mejo.2017.01.014
Yun Liang Mitra TLei Ju (2015)Instruction Cache Locking Using Temporal Reuse ProfileIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2015.241832034:9(1387-1400)Online publication date: 1-Sep-2015
https://dl.acm.org/doi/10.1109/TCAD.2015.2418320
Själander MMartonosi MKaxiras S(2014)Power-Efficient Computer Architectures: Recent AdvancesSynthesis Lectures on Computer Architecture10.2200/S00611ED1V01Y201411CAC0309:3(1-96)Online publication date: Dec-2014
https://doi.org/10.2200/S00611ED1V01Y201411CAC030
Liang YMitra T(2013)An analytical approach for fast and accurate design space exploration of instruction cachesACM Transactions on Embedded Computing Systems10.1145/2539036.253903913:3(1-29)Online publication date: 24-Dec-2013
https://dl.acm.org/doi/10.1145/2539036.2539039
Jain G(2013)Memory Models for Embedded Multicore ArchitectureReal World Multicore Embedded Systems10.1016/B978-0-12-416018-7.00004-3(75-116)Online publication date: 2013
https://doi.org/10.1016/B978-0-12-416018-7.00004-3
Yoon JYu CKim DKim L(2011)A dual-shader 3-D graphics processor with fast 4-D vector inner product units and power-aware texture cacheIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.203892219:4(525-537)Online publication date: 1-Apr-2011
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Aparicio LSegarra JRodríguez CViñals V(2011)Improving the WCET computation in the presence of a lockable instruction cache in multitasking real-time systemsJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2010.08.00857:7(695-706)Online publication date: 1-Aug-2011
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