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The fuzzy barrier: a mechanism for high speed synchronization of processors

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Rajiv GuptaAuthors Info & Claims

ASPLOS III: Proceedings of the third international conference on Architectural support for programming languages and operating systems

Pages 54 - 63

https://doi.org/10.1145/70082.68187

Published: 01 April 1989 Publication History

Abstract

Parallel programs are commonly written using barriers to synchronize parallel processes. Upon reaching a barrier, a processor must stall until all participating processors reach the barrier. A software implementation of the barrier mechanism using shared variables has two major drawbacks. Firstly, the execution of the barrier may be slow as it may not only require execution of several instructions and but also result in hot-spot accesses. Secondly, processors that are stalled waiting for other processors to reach the barrier are essentially idling and cannot do any useful work. In this paper, the notion of the fuzzy barrier is presented, that avoids the above drawbacks. The first problem is avoided by implementing the mechanism in hardware. The second problem is solved by extending the barrier concept to include a region of statements that can be executed by a processor while it awaits synchronization. The barrier regions are constructed by a compiler and consist of several instructions such that a processor is ready to synchronize upon reaching the first instruction in this region and must synchronize before exiting the region. When synchronization does occur, the processors could be executing at any point in their respective barrier regions. The larger the barrier region, the more likely it is that none of the processors will have to stall. Preliminary investigations show that barrier regions can be large and the use of program transformations can significantly increase their size. Examples of situations where such a mechanism can result in improved performance are presented. Results based on a software implementation of the fuzzy barrier on the Encore multiprocessor indicate that the synchronization overhead can be greatly reduced using the mechanism.

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Garza AParra CScherson I(2021)Non-Blocking Technique for Parallel Algorithms with Global Barrier Synchronization2021 International Conference on Computational Science and Computational Intelligence (CSCI)10.1109/CSCI54926.2021.00334(1759-1764)Online publication date: Dec-2021
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The fuzzy barrier: a mechanism for high speed synchronization of processors
Special issue: Proceedings of ASPLOS-III: the third international conference on architecture support for programming languages and operating systems

Parallel programs are commonly written using barriers to synchronize parallel processes. Upon reaching a barrier, a processor must stall until all participating processors reach the barrier. A software implementation of the barrier mechanism using ...
Support for speculative execution in high-performance processors
Support for Speculative Execution in High-Performance Processors

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cover image ACM Conferences

ASPLOS III: Proceedings of the third international conference on Architectural support for programming languages and operating systems

April 1989

303 pages

ISBN:0897913000

DOI:10.1145/70082

Chairman:
Joel Emer,
General Chair:
John Hennessy
Stanford University

ACM SIGARCH Computer Architecture News Volume 17, Issue 2
Special issue: Proceedings of ASPLOS-III: the third international conference on architecture support for programming languages and operating systems
April 1989
291 pages
ISSN:0163-5964
DOI:10.1145/68182
Editor:
Joel Emer
Issue’s Table of Contents

Copyright © 1989 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 April 1989

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ASPLOS89: Int'l Conference on Architecture Support for Programming Lang & Operating Systems

April 3 - 6, 1989

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Cited By

Garza AParra CScherson I(2021)Non-Blocking Technique for Parallel Algorithms with Global Barrier Synchronization2021 International Conference on Computational Science and Computational Intelligence (CSCI)10.1109/CSCI54926.2021.00334(1759-1764)Online publication date: Dec-2021
https://doi.org/10.1109/CSCI54926.2021.00334
Jun JPaik YMin GKim SHan Y(2019)Fault Tolerance Technique Offlining Faulty Blocks by Heap Memory ManagementACM Transactions on Design Automation of Electronic Systems10.1145/332907924:4(1-25)Online publication date: 5-Jun-2019
https://dl.acm.org/doi/10.1145/3329079
Yamashita KKamada T(2016)Introducing a Multithread and Multistage Mechanism for the Global Load Balancing Library of X10Journal of Information Processing10.2197/ipsjjip.24.41624:2(416-424)Online publication date: 2016
https://doi.org/10.2197/ipsjjip.24.416
Huang JPrabhu PJablin TGhosh SApostolakis SLee JAugust DZaks AMendelson BRauchwerger LHwu W(2016)Speculatively Exploiting Cross-Invocation ParallelismProceedings of the 2016 International Conference on Parallel Architectures and Compilation10.1145/2967938.2967959(207-221)Online publication date: 11-Sep-2016
https://dl.acm.org/doi/10.1145/2967938.2967959
Wang JAbu-Ghazaleh NPonomarev D(2015)AIRACM Transactions on Modeling and Computer Simulation10.1145/270142025:3(1-25)Online publication date: 16-Apr-2015
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Jung HHan HFekete AHeiser GYeom H(2014)A Scalable Lock Manager for MulticoresACM Transactions on Database Systems10.1145/2691190.269119239:4(1-29)Online publication date: 30-Dec-2014
https://dl.acm.org/doi/10.1145/2691190.2691192
Lo SLee CKao QChung IChung Y(2014)Improving GPU Memory Performancewith Artificial Barrier SynchronizationIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2013.13325:9(2342-2352)Online publication date: Sep-2014
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Malkis ABanerjee A(2014)On Automation in the Verification of Software BarriersJournal of Automated Reasoning10.1007/s10817-013-9290-952:3(275-329)Online publication date: 1-Mar-2014
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Poole SShamis PWelch APophale SVenkata MHernandez OKoenig GCurtis THsu C(2014)OpenSHMEM Extensions and a Vision for Its Future DirectionProceedings of the First Workshop on OpenSHMEM and Related Technologies. Experiences, Implementations, and Tools - Volume 835610.1007/978-3-319-05215-1_11(149-162)Online publication date: 4-Mar-2014
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Scott M(2013)Shared-Memory SynchronizationSynthesis Lectures on Computer Architecture10.2200/S00499ED1V01Y201304CAC0238:2(1-221)Online publication date: 12-Jun-2013
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