skip to main content
10.1145/3649329.3656496acmconferencesArticle/Chapter ViewAbstractPublication PagesdacConference Proceedingsconference-collections
research-article
Open access

ModSRAM: Algorithm-Hardware Co-Design for Large Number Modular Multiplication in SRAM

Published: 07 November 2024 Publication History

Abstract

Elliptic curve cryptography (ECC) is widely used in security applications such as public key cryptography (PKC) and zero-knowledge proofs (ZKP). ECC is composed of modular arithmetic, where modular multiplication takes most of the processing time. Computational complexity and memory constraints of ECC limit the performance. Therefore, hardware acceleration on ECC is an active field of research. Processing-in-memory (PIM) is a promising approach to tackle this problem. In this work, we design ModSRAM, the first 8T SRAM PIM architecture to compute large-number modular multiplication efficiently. In addition, we propose R4CSA-LUT, a new algorithm that reduces the cycles for an interleaved algorithm and eliminates carry propagation for addition based on look-up tables (LUT). ModSRAM is co-designed with R4CSA-LUT to support modular multiplication and data reuse in memory with 52% cycle reduction compared to prior works with only 32% area overhead.

References

[1]
Amogh Agrawal et al. 2018. X-SRAM: Enabling In-Memory Boolean Computations in CMOS Static Random Access Memories. IEEE Transactions on Circuits and Systems I: Regular Papers 65, 12 (2018), 4219--4232.
[2]
Paul Barrett. 1987. Implementing the Rivest Shamir and Adleman Public Key Encryption Algorithm on a Standard Digital Signal Processor. In Advances in Cryptology --- CRYPTO' 86, Andrew M. Odlyzko (Ed.).
[3]
G.R. Blakely. 1983. A Computer Algorithm for Calculating the Product AB Modulo M. IEEE Trans. Comput. C-32, 5 (1983), 497--500.
[4]
ANDREW D. BOOTH. 1951. A SIGNED BINARY MULTIPLICATION TECHNIQUE. The Quarterly Journal of Mechanics and Applied Mathematics (1951).
[5]
Fan Chen et al. 2018. ReGAN: A pipelined ReRAM-based accelerator for generative adversarial networks. In 2018 23rd ASP-DAC.
[6]
Lily Chen et al. 2023. Digital Signature Standard (DSS). https://tsapps.nist.gov/publication/get_pdf.cfm?pub_id=935202
[7]
Shafi Goldwasser et al. 1989. The Knowledge Complexity of Interactive Proof Systems. SIAM J. Comput. 18, 1 (1989), 186--208.
[8]
Khalid Javeed and Xiaojun Wang. 2014. Radix-4 and radix-8 booth encoded interleaved modular multipliers over general Fp. In 2014 24th FPL.
[9]
Houxiang Ji et al. 2018. ReCom: An efficient resistive accelerator for compressed deep neural networks. In DATE.
[10]
Neal Koblitz. 1987. Elliptic curve cryptosystems. Mathematics of computation 48, 177 (1987), 203--209.
[11]
Kyeongho Lee et al. 2020. Bit Parallel 6T SRAM In-memory Computing with Reconfigurable Bit-Precision. In 2020 57th ACM/IEEE DAC.
[12]
Dai Li et al. 2022. MeNTT: A Compact and Efficient Processing-in-Memory Number Theoretic Transform (NTT) Accelerator. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 30, 5 (2022), 579--588.
[13]
Mengyuan Li et al. 2023. Accelerating Polynomial Modular Multiplication with Crossbar-Based Compute-in-Memory. arXiv preprint arXiv:2307.14557 (2023).
[14]
Ziru Li et al. 2022. ASTERS: adaptable threshold spike-timing neuromorphic design with twin-column ReRAM synapses. In Proceedings of the 59th ACM/IEEE Design Automation Conference (San Francisco, California) (DAC '22). 1099--1104.
[15]
Oleg Mazonka et al. 2022. Fast and Compact Interleaved Modular Multiplication Based on Carry Save Addition. In Proceedings of the 41st IEEE/ACM ICCAD.
[16]
A. C. Mert et al. 2020. Parametric-ntt. https://github.com/acmert/parametric-ntt.
[17]
Ahmet Can Mert et al. 2022. An Extensive Study of Flexible Design Methods for the Number Theoretic Transform. IEEE Trans. Comput. 71, 11 (2022), 2829--2843.
[18]
Peter L Montgomery. 1985. Modular multiplication without trial division. Mathematics of computation 44, 170 (1985), 519--521.
[19]
Hamid Nejatollahi et al. 2020. CryptoPIM: In-memory Acceleration for Lattice-based Cryptographic Hardware. In 2020 57th ACM/IEEE DAC.
[20]
Yongmo Park et al. 2022. RM-NTT: An RRAM-Based Compute-in-Memory Number Theoretic Transform Accelerator. IEEE Journal on Exploratory SolidState Computational Devices and Circuits 8, 2 (2022), 93--101.
[21]
J. M. Pollard. 1971. The fast Fourier transform in a finite field. Math. Comp. 25 (1971), 365--374. https://api.semanticscholar.org/CorpusID:123174851
[22]
R. L. Rivest, A. Shamir, and L. Adleman. 1978. A Method for Obtaining Digital Signatures and Public-Key Cryptosystems. Commun. ACM (feb 1978).
[23]
Amitesh Sridharan et al. 2022. A 1.23-GHz 16-kb Programmable and Generic Processing-in-SRAM Accelerator in 65nm. In IEEE 48th ESSCIRC.
[24]
B. Wicht et al. 2004. Yield and speed optimization of a latch-type voltage sense amplifier. IEEE Journal of Solid-State Circuits 39, 7 (2004), 1148--1158.
[25]
Bonan Yan et al. 2019. RRAM-based Spiking Nonvolatile Computing-In-Memory Processing Engine with Precision-Configurable In Situ Nonlinear Activation. In 2019 Symposium on VLSI Technology.
[26]
Jingyao Zhang et al. 2023. BP-NTT: Fast and Compact in-SRAM Number Theoretic Transform with Bit-Parallel Modular Multiplication. arXiv:2303.00173
[27]
Yiqun Zhang et al. 2018. Recryptor: A Reconfigurable Cryptographic Cortex-M0 Processor With In-Memory and Near-Memory Computing for IoT Security. IEEE Journal of Solid-State Circuits 53, 4 (2018), 995--1005.
[28]
Ye Zhang et al. 2021. PipeZK: Accelerating Zero-Knowledge Proof with a Pipelined Architecture. In 2021 ACM/IEEE 48th ISCA. 416--428.
[29]
Qilin Zheng et al. 2020. Lattice: An ADC/DAC-less ReRAM-based Processing-In-Memory Architecture for Accelerating Deep Convolution Neural Networks. In 2020 57th ACM/IEEE DAC.

Recommendations

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences
DAC '24: Proceedings of the 61st ACM/IEEE Design Automation Conference
June 2024
2159 pages
ISBN:9798400706011
DOI:10.1145/3649329
This work is licensed under a Creative Commons Attribution International 4.0 License.

Sponsors

In-Cooperation

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 07 November 2024

Check for updates

Qualifiers

  • Research-article

Funding Sources

  • NSF

Conference

DAC '24
Sponsor:
DAC '24: 61st ACM/IEEE Design Automation Conference
June 23 - 27, 2024
CA, San Francisco, USA

Acceptance Rates

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

Upcoming Conference

DAC '25
62nd ACM/IEEE Design Automation Conference
June 22 - 26, 2025
San Francisco , CA , USA

Contributors

Other Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

  • 0
    Total Citations
  • 166
    Total Downloads
  • Downloads (Last 12 months)166
  • Downloads (Last 6 weeks)102
Reflects downloads up to 22 Jan 2025

Other Metrics

Citations

View Options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Login options

Media

Figures

Other

Tables

Share

Share

Share this Publication link

Share on social media