Introduction to the FPL 2021 Special Section

The International Conference on Field-Programmable Logic and Applications (FPL) was the first and remains the largest conference covering the rapidly growing area of field-programmable logic and reconfigurable computing. During the past 30 years, many of the advances in reconfigurable system architectures, applications, embedded processors, and design automation methods and tools were first published in the proceedings of the FPL conference series. The conference objective is to bring together researchers and practitioners from both academia and industry and from around the world.

The 31st edition of the FPL (2021) took place from August 30 till September 3, 2021. It is the second FPL conference that had to be organized as a virtual event due to the COVID-19 pandemic.

The purpose of this Special Section is to provide an insight into current research and development in aspects related to Field-Programmable Gate Array (FPGA) applications, FPGA technology, and FPGA programming models and tools. This Special Section includes three papers that were presented in the 2021 edition of the conference. The three articles were appropriately selected (based on their quality) to cover various topics of the conference.

The article “Exploring FPGA Switch-Blocks without Explicit Pattern Listing” proposes a solution to the problem of increased resistance of lower metal layers, which has a direct impact on the physical aspects of FPGA switch-blocks. The need to navigate a design space where each individual switch can have a significant impact on the FPGA's performance in turn makes automated switch-pattern exploration techniques increasingly appealing. However, most existing exploration techniques have a fundamental limitation: they use the CAD tools as a black box to evaluate the performance of explicitly listed switch-patterns. Because there is limited time to route a modern circuit on a single architecture, the resulting situation where only a small number of switch-patterns can be explicitly tested quickly becomes a major issue while facing a large design space. This article presents a technique that removes this fundamental limitation by making the entire design space visible to the router and letting it choose the switches to be added to the pattern, based on the requirements of the circuits being routed. The key to preventing the router from selecting arbitrary switches that would render the final pattern excessively large is to apply the same negotiation principle used by the router to remove congestion, just in the opposite direction, to make the signals reach a consensus on which switches are worthy of being included in the final switch-pattern.

The article “An Efficient FPGA-based Depthwise Separable Convolutional Neural Network Accelerator with Hardware Pruning” presents an efficient inference accelerator on FPGA for CNNs with depthwise separable convolutions (DSCs). To improve the accelerator efficiency, the authors make four contributions: (i) an efficient convolution engine with multiple strategies for exploiting parallelism and a configurable adder tree is designed to support three types of convolution operations; (ii) a dedicated architecture combined with input buffers is designed for the bottleneck network structure to reduce data transmission time; (iii) a hardware padding scheme to eliminate invalid padding operations is proposed; (iv) a hardware-assisted pruning method is developed to support online tradeoff between model accuracy and power consumption. Experimental results show that for MobileNetV2 the accelerator achieves significant energy efficiency improvements over CPU and GPU implementations.

Finally, the article “Eciton: Very Low-Power Recurrent Neural Network Accelerator for Real-Time Inference at the Edge” proposes Eciton, a very low-power recurrent neural network accelerator for time series data within low-power edge sensor nodes, achieving real-time inference with a power consumption of 17 mW under load. Eciton reduces memory and chip resource requirements via 8-bit quantization and hard sigmoid activation, allowing the accelerator as well as the recurrent neural network model parameters to fit in a low-cost, low-power Lattice iCE40 UP5K FPGA. The proposed accelerator demonstrates real-time processing at a very low power consumption with minimal loss of accuracy on multiple inference scenarios with differing characteristics, while achieving competitive power efficiency against the state-of-the-art of similar scale. The resulting power budget of the sensor node is small enough to be powered by a power harvester, potentially allowing it to run continuously without a battery or periodic maintenance.

We express our sincere gratitude to all who contributed in any way to produce this Special Section. We would like to thank all the authors for their valuable contributions to this Special Section. We would also like to acknowledge and thank the reviewers for their valuable efforts, as well as our FPL 2021 sponsors for supporting the conference: our Platinum sponsors (Cologne Chip AG, Intel, and Xilinx), our Gold sponsors (Cadence and Synopsys), our Silver sponsors (Fraunhofer IPMS and Two Sigma), and our Bronze sponsors (Maxeler and Inaccel). We hope that this Special Section will serve as a valuable resource for the TRETS community.