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An architecture for the direct execution of the Forth programming language

Authors:

John R. Hayes,

Martin E. Fraeman,

Robert L. Williams,

Thomas ZarembaAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 15, Issue 5

Pages 42 - 49

https://doi.org/10.1145/36177.36182

Published: 01 October 1987 Publication History

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Abstract

We have developed a simple direct execution architecture for a 32 bit Forth microprocessor. The processor can directly access a linear address space of over 4 gigawords. Two instruction types are defined; a subroutine call, and a user defined microcode instruction. On-chip stack caches allow most Forth primitives to execute in a single cycle.

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Fraeman, M. E., Hayes, J. R., Williams, R. L., Zaremba, T. "A 32 Bit Architecture For Direct Execution of Forth", Proc. of the Eighth FORMAL Conference, 1986.

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Bosse S(2024)A Virtual Machine Platform Providing Machine Learning as a Programmable and Distributed Service for IoT and Edge On-Device Computing: Architecture, Transformation, and Evaluation of Integer DiscretizationAlgorithms10.3390/a1708035617:8(356)Online publication date: 15-Aug-2024
https://doi.org/10.3390/a17080356
Bosse SPolle C(2023)Tiny Machine Learning Virtualization for IoT and Edge Computing using the REXA VM2023 10th International Conference on Future Internet of Things and Cloud (FiCloud)10.1109/FiCloud58648.2023.00026(122-129)Online publication date: 14-Aug-2023
https://doi.org/10.1109/FiCloud58648.2023.00026
Lopriore L(1993)A data cache for Prolog architecturesFuture Generation Computer Systems10.1016/0167-739X(93)90013-F9:3(219-234)Online publication date: 1-Sep-1993
https://dl.acm.org/doi/10.1016/0167-739X%2893%2990013-F
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An architecture for the direct execution of the Forth programming language

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An architecture for the direct execution of the Forth programming language
ASPLOS II: Proceedings of the second international conference on Architectual support for programming languages and operating systems

We have developed a simple direct execution architecture for a 32 bit Forth microprocessor. The processor can directly access a linear address space of over 4 gigawords. Two instruction types are defined; a subroutine call, and a user defined microcode ...
An architecture for the direct execution of the Forth programming language

We have developed a simple direct execution architecture for a 32 bit Forth microprocessor. The processor can directly access a linear address space of over 4 gigawords. Two instruction types are defined; a subroutine call, and a user defined microcode ...
An architecture for the direct execution of the Forth programming language

We have developed a simple direct execution architecture for a 32 bit Forth microprocessor. The processor can directly access a linear address space of over 4 gigawords. Two instruction types are defined; a subroutine call, and a user defined microcode ...

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Information & Contributors

Information

Published In

cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 15, Issue 5

Oct. 1987

189 pages

ISSN:0163-5964

DOI:10.1145/36177

Editor:
Randy H. Katz
Univ. of California, Berkeley

Issue’s Table of Contents

ASPLOS II: Proceedings of the second international conference on Architectual support for programming languages and operating systems
October 1987
205 pages
ISBN:0818608056
DOI:10.1145/36206
Editor:
Randy Katz
Univ. of California, Berkeley
,
General Chair:
Martin Freeman
Stanford University and Philips/Signetics

Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for third-party components of this work must be honored. For all other uses, contact the Owner/Author.

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 October 1987

Published in SIGARCH Volume 15, Issue 5

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Cited By

View all

Bosse S(2024)A Virtual Machine Platform Providing Machine Learning as a Programmable and Distributed Service for IoT and Edge On-Device Computing: Architecture, Transformation, and Evaluation of Integer DiscretizationAlgorithms10.3390/a1708035617:8(356)Online publication date: 15-Aug-2024
https://doi.org/10.3390/a17080356
Bosse SPolle C(2023)Tiny Machine Learning Virtualization for IoT and Edge Computing using the REXA VM2023 10th International Conference on Future Internet of Things and Cloud (FiCloud)10.1109/FiCloud58648.2023.00026(122-129)Online publication date: 14-Aug-2023
https://doi.org/10.1109/FiCloud58648.2023.00026
Lopriore L(1993)A data cache for Prolog architecturesFuture Generation Computer Systems10.1016/0167-739X(93)90013-F9:3(219-234)Online publication date: 1-Sep-1993
https://dl.acm.org/doi/10.1016/0167-739X%2893%2990013-F
Ertl M(1995)Stack caching for interpretersACM SIGPLAN Notices10.1145/223428.20716530:6(315-327)Online publication date: 1-Jun-1995
https://dl.acm.org/doi/10.1145/223428.207165
Ertl MWall D(1995)Stack caching for interpretersProceedings of the ACM SIGPLAN 1995 conference on Programming language design and implementation10.1145/207110.207165(315-327)Online publication date: 18-Jun-1995
https://dl.acm.org/doi/10.1145/207110.207165
Chandross JJagadish HAsthana APatt Y(1988)The trap as a control flow mechanismProceedings of the 21st annual workshop on Microprogramming and microarchitecture10.5555/62504.62527(50-52)Online publication date: 3-Jan-1988
https://dl.acm.org/doi/10.5555/62504.62527
Good P(1988)Structuring an instruction cacheACM SIGARCH Computer Architecture News10.1145/48675.4868116:3(40-43)Online publication date: 1-Jun-1988
https://dl.acm.org/doi/10.1145/48675.48681
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