Ring Oscillator based on Integer Dynamic Programming

As electronic products are updated, chips need to be constantly optimized for design, and the ring oscillator is one of the essential structures. By studying the oscillator area, power consumption and other elements, the best design solution to meet the relevant performance is investigated. It plays a role in promoting the development of chip industry. In this paper, we first model the frequency and area of the ring oscillator to design it. The optimal size is obtained, and then the power consumption is optimized for the design. The relationship between the energy consumption of the ring oscillator and the size and number of inverters is first analyzed by the energy consumption principle, and then an integer programming dynamic model is further developed. Finally, the concept of multiple wafers is introduced to optimize the chip stitching. This allows more ring oscillators to be placed on the last chip position with minimum power consumption. In this paper, the optimization is performed using the Condor algorithm to obtain the optimal design solution in terms of area and power consumption. The results show that the optimal design solution is 3 inverters with 101 nm gate length, 115 nm NMOS gate width, 120 nm PMOS gate width, and 3406018 number of ring oscillators on the last chip.

CCS Concepts:Hardware∼ Integrated circuits∼ Semiconductor memory∼ Static memory