Guest Editorial: Computation-In-Memory (CIM): from Device to Applications

Today's emerging applications are extremely demanding in terms of storage and computing power. For instance, the Internet-of-things (IoT) combined with edge computing will transform the future. They will not only impact all aspects of our life but also change the Integrated Circuit (IC) and computer world. Emerging applications require computing power, which was typical of supercomputers a few years ago, but with constraints on size, power consumption, and guaranteed response time that are typical of the embedded applications. Both today's computer architectures and device technologies (used to manufacture them) are facing major challenges, making them incapable of delivering the required functionalities and features. Computers are facing the three well-known walls [1]: (1) the Memory wall, due to the increasing gap between processor and memory speeds, and the limited memory bandwidth, making memory access the killer of performance and power for memory access–dominated applications, for example, big-data; (2) the Instruction Level parallelism (ILP) wall, due to the increasing difficulty in finding enough parallelism in software/code that has to run on a parallel hardware, being the mainstream today; and (3) the Power wall, as the practical power limit for cooling is reached, meaning no further increase in CPU clock speed. On the other hand, nanoscale complementary metal-oxide-semiconductor (CMOS) technology, which has been the enabler of the computing revolution, also faces three walls [2]: (1) the Reliability wall, as technology scaling leads to reduced device lifetime and higher failure rate; (2) the Leakage wall, as the static power is becoming dominant at smaller technologies (due to volatile technology and lower Vdd) and may even be more than the dynamic power; and (3) the Cost wall, as the cost per device via pure geometric scaling of process technology is plateauing. All of these have led to the slowdown of traditional device scaling. In order for computing systems to continue to deliver sustainable benefits to society for the foreseeable future, alternative computing architectures and notions have to be explored in the light of emerging new device technologies.

Computation-in-memory (CIM) is one of the alternative computing architectures that has been attracting a lot of attention, as it seems to have a huge potential in delivering order-of-magnitude improvement in terms of energy efficiency, for example [3–5]. CIM may make use of traditional memory technologies such as SRAM [6, 7] and DRAM [8, 9] as well as of emerging device and memory technologies such as resistive random access memory (RRAM) [10, 11], spin-transfer torque magnetic random-access memory (STT-MRAM) [12, 13], Pulse-code modulation  PCM [14, 15], or even ferroelectric transistor (FeFET) [16, 17]. Research on CIM has been attracting a lot of attention and has been exploring different aspects of the computing engine design stack such as device, circuit design, architectures, compilers, automation and tools, algorithms, and applications.

This special issue intends to capture the state-of-the-art and explore different aspects related to CIM full-stack design and show its potential applications and benefits. The inherent characteristics of CIM force the revision of existing design methods. From all of the received submissions from experts in the field, only 12 could be accepted to be included in this issue. These 12 papers cover four major aspects related to CIM: (1) circuit design concepts, (2) architectures, (3) applications, and (4) automation tools.

Three papers are related to circuit design concepts. The paper titled “A Voltage Controlled Oscillation-Based ADC Design for Computation-in-Memory Architectures Using Emerging ReRAMs” by A. Singh et al. proposes a dedicated power- and area-efficient ADC for approximate vector-matrix calculations. The paper titled “Accuracy and Resiliency of Analog Computein-Memory Inference Engines” by Z. Wan et al. analyzes the usage of CIM architecture based on nonvolatile devices for the scalable Deep Neural Network (DNN) and proposes a simulation framework that estimates the effect of the device nonidealities on the overall performance and resiliency of the DNN. The paper titled “Impact of On-Chip Interconnect on In-Memory Acceleration of Deep Neural Networks” by G. Krishnan et al. explores different on-chip interconnect designs for SRAM- as well for RRAM-based CIM architectures for a range of DNNs.

Five papers are related to architectures. The paper titled “Accelerating On-Chip Training with Ferroelectric-based Hybrid Precision Synapse” by Y. Luo et al. proposes an accelerator hardware architecture based on FeFET for DNN on-chip training and higher integration density. The paper titled “A Spiking Neuromorphic Architecture Using Gated-RRAM for Associative Memory” by A. Jones et al. uses gated RRAM devices as synapses alongside CMOS-based neurons to build spiking neuromorphic architecture for dense associative memory in real time. The paper titled “COSMO: Computing with Stochastic Numbers in Memory” by S. Gupta et al. exploits the inherent properties of RRAM-based CIM to support various stochastic encodings and operation while maximizing the performance and energy efficiency. The paper titled “Unsupervised Digit Recognition Using Cosine Similarity in a Neuromemristive Competitive Learning System” by B.-W. Ku et al. discusses a two-layer, fully connected, memristor-based neural network architecture for manipulating cosine similarity in a hard winner-take-all. The paper titled “STAP: An Architecture and Design Tool for Automata Processing on Memristor TCAMs” by J.-P. de Lima et al. presents an automata-specific reconfigurable fabric implemented using resistive ternary content-addressable memory (TCAM) that enables efficient implementation through proper encoding and mapping methods.

One paper is related to applications. It is titled “Towards a Truly Integrated Vector Processing Unit for Memory-Bound Applications Based on a Cost-Competitive Computational SRAM Design Solution” by M. Kooli et al. It presents the benefits of using the computational SRAM design for a cryptography application (AES) and a convolutional neural network.

Three papers are related to automation and computer-aided design tools. The first is titled “Parallel Computing of Graph-Based functions in ReRAM” by S. Fröhlich et al. It presents efficient synthesis strategies for Boolean functions using graph-based representations. The second paper, titled “Early Design Space Exploration Framework for Memristive Crossbar Arrays” by S. Katkoori et al., proposes a framework based on VHSIC Hardware Description Language to quickly perform behavioral simulation of any large memristive crossbar array. The third paper, titled “The BitletModel: A Parameterized AnalyticalModel to⟨?PMU?⟩ Compare PIM and CPU Systems” by A. Eliahu et al., proposes an analytic model for CIM performance evaluation.