research-article

ASTERS: adaptable threshold spike-timing neuromorphic design with twin-column ReRAM synapses

Authors:

Yiran ChenAuthors Info & Claims

DAC '22: Proceedings of the 59th ACM/IEEE Design Automation Conference

Pages 1099 - 1104

https://doi.org/10.1145/3489517.3530591

Published: 23 August 2022 Publication History

Abstract

Complex event-driven neuron dynamics was an obstacle to implementing efficient brain-inspired computing architectures with VLSI circuits. To solve this problem and harness the event-driven advantage, we propose ASTERS, a resistive random-access memory (ReRAM) based neuromorphic design to conduct the time-to-first-spike SNN inference. In addition to the fundamental novel axon and neuron circuits, we also propose two techniques through hardware-software co-design: "Multi-Level Firing Threshold Adjustment" to mitigate the impact of ReRAM device process variations, and "Timing Threshold Adjustment" to further speed up the computation. Experimental results show that our cross-layer solution ASTERS achieves more than 34.7% energy savings compared to the existing spiking neuromorphic designs, meanwhile maintaining 90.1% accuracy under the process variations with a 20% standard deviation.

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Cited By

Wang SGao YLi YZhang WYu YWang BLin NChen HZhang YJiang YWang DChen JDai PJiang HLin PZhang XQi XXu XSo HWang ZShang DLiu QCheng KLiu M(2025)Random resistive memory-based deep extreme point learning machine for unified visual processingNature Communications10.1038/s41467-025-56079-316:1Online publication date: 23-Jan-2025
https://doi.org/10.1038/s41467-025-56079-3
Li ZZheng QKu JTaylor BLi H(2024)TFSRAM: A 249.8TOPS/W Timing-to-First-Spike Compute-in-Memory Neuromorphic Processing Engine With Twin-Column SRAM SynapsesIEEE Transactions on Circuits and Systems for Artificial Intelligence10.1109/TCASAI.2024.34526491:1(26-36)Online publication date: Sep-2024
https://doi.org/10.1109/TCASAI.2024.3452649
Yang XLi SZheng QChen YTakahashi A(2023)Improving the Robustness and Efficiency of PIM-Based Architecture by SW/HW Co-DesignProceedings of the 28th Asia and South Pacific Design Automation Conference10.1145/3566097.3568358(618-623)Online publication date: 16-Jan-2023
https://dl.acm.org/doi/10.1145/3566097.3568358
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cover image ACM Conferences

DAC '22: Proceedings of the 59th ACM/IEEE Design Automation Conference

July 2022

1462 pages

ISBN:9781450391429

DOI:10.1145/3489517

General Chair:
Rob Oshana
NXP

Copyright © 2022 ACM.

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Published: 23 August 2022

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DAC '22: 59th ACM/IEEE Design Automation Conference

July 10 - 14, 2022

California, San Francisco

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Cited By

Wang SGao YLi YZhang WYu YWang BLin NChen HZhang YJiang YWang DChen JDai PJiang HLin PZhang XQi XXu XSo HWang ZShang DLiu QCheng KLiu M(2025)Random resistive memory-based deep extreme point learning machine for unified visual processingNature Communications10.1038/s41467-025-56079-316:1Online publication date: 23-Jan-2025
https://doi.org/10.1038/s41467-025-56079-3
Li ZZheng QKu JTaylor BLi H(2024)TFSRAM: A 249.8TOPS/W Timing-to-First-Spike Compute-in-Memory Neuromorphic Processing Engine With Twin-Column SRAM SynapsesIEEE Transactions on Circuits and Systems for Artificial Intelligence10.1109/TCASAI.2024.34526491:1(26-36)Online publication date: Sep-2024
https://doi.org/10.1109/TCASAI.2024.3452649
Yang XLi SZheng QChen YTakahashi A(2023)Improving the Robustness and Efficiency of PIM-Based Architecture by SW/HW Co-DesignProceedings of the 28th Asia and South Pacific Design Automation Conference10.1145/3566097.3568358(618-623)Online publication date: 16-Jan-2023
https://dl.acm.org/doi/10.1145/3566097.3568358
Yan BYang YHuang R(2023)Memristive dynamics enabled neuromorphic computing systemsScience China Information Sciences10.1007/s11432-023-3739-066:10Online publication date: 18-Sep-2023
https://doi.org/10.1007/s11432-023-3739-0

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