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Wattch: a framework for architectural-level power analysis and optimizations

Authors:

Margaret MartonosiAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 28, Issue 2

Pages 83 - 94

https://doi.org/10.1145/342001.339657

Published: 01 May 2000 Publication History

Abstract

Power dissipation and thermal issues are increasingly significant in modern processors. As a result, it is crucial that power/performance tradeoffs be made more visible to chip architects and even compiler writers, in addition to circuit designers. Most existing power analysis tools achieve high accuracy by calculating power estimates for designs only after layout or floorplanning are complete. In addition to being available only late in the design process, such tools are often quite slow, which compounds the difficulty of running them for a large space of design possibilities.

This paper presents Wattch, a framework for analyzing and optimizing microprocessor power dissipation at the architecture-level. Wattch is 1000X or more faster than existing layout-level power tools, and yet maintains accuracy within 10% of their estimates as verified using industry tools on leading-edge designs. This paper presents several validations of Wattch's accuracy. In addition, we present three examples that demonstrate how architects or compiler writers might use Wattch to evaluate power consumption in their design process.

We see Wattch as a complement to existing lower-level tools; it allows architects to explore and cull the design space early on, using faster, higher-level tools. It also opens up the field of power-efficient computing to a wider range of researchers by providing a power evaluation methodology within the portable and familiar SimpleScalar framework.

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Index Terms

Wattch: a framework for architectural-level power analysis and optimizations
1. Hardware
  1. Hardware validation

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Information

Published In

cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 28, Issue 2

Special Issue: Proceedings of the 27th annual international symposium on Computer architecture (ISCA '00)

May 2000

325 pages

ISSN:0163-5964

DOI:10.1145/342001

Chairmen:
Alan Berenbaum
Lucent Technologies, Berkeley Heights, NJ
,
Joel Emer
Compaq Computer Corp., Palo Alto, CA

Issue’s Table of Contents

ISCA '00: Proceedings of the 27th annual international symposium on Computer architecture
June 2000
327 pages
ISBN:1581132328
DOI:10.1145/339647
Chairmen:
Alan Berenbaum
Lucent Technologies
,
Joel Emer
Compaq Computer Corp.

Copyright © 2000 ACM.

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Association for Computing Machinery

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Publication History

Published: 01 May 2000

Published in SIGARCH Volume 28, Issue 2

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https://doi.org/10.1016/j.simpat.2024.103032
Rana MMamun QIslam R(2024)Balancing Security and Efficiency: A Power Consumption Analysis of a Lightweight Block CipherElectronics10.3390/electronics1321432513:21(4325)Online publication date: 4-Nov-2024
https://doi.org/10.3390/electronics13214325
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