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Effects of inductance on the propagation delay and repeater insertion in VLSI circuits

Authors:

Yehea I. Ismail,

Eby G. FriedmanAuthors Info & Claims

DAC '99: Proceedings of the 36th annual ACM/IEEE Design Automation Conference

Pages 721 - 724

https://doi.org/10.1145/309847.310042

Published: 01 June 1999 Publication History

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Cited By

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Jiang ZHu SHu JLi ZShi WHassoun S(2006)A new RLC buffer insertion algorithmProceedings of the 2006 IEEE/ACM international conference on Computer-aided design10.1145/1233501.1233614(553-557)Online publication date: 5-Nov-2006
https://dl.acm.org/doi/10.1145/1233501.1233614
Tsuchiya AHashimoto MOnodera HHirose F(2006)Interconnect RL extraction at a single representative frequencyProceedings of the 2006 Asia and South Pacific Design Automation Conference10.1145/1118299.1118424(515-520)Online publication date: 24-Jan-2006
https://dl.acm.org/doi/10.1145/1118299.1118424
Jiang ZHu SHu JLi ZShi W(2006)A New RLC Buffer Insertion Algorithm2006 IEEE/ACM International Conference on Computer Aided Design10.1109/ICCAD.2006.320173(553-557)Online publication date: Nov-2006
https://doi.org/10.1109/ICCAD.2006.320173
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Index Terms

Effects of inductance on the propagation delay and repeater insertion in VLSI circuits
1. Applied computing
  1. Physical sciences and engineering
2. Hardware
  1. Very large scale integration design

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Effects of inductance on the propagation delay and repeater insertion in VLSI circuits

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Published In

DAC '99: Proceedings of the 36th annual ACM/IEEE Design Automation Conference

June 1999

1000 pages

ISBN:1581131097

DOI:10.1145/309847

Editor:
Mary Jane Irwin

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 June 1999

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DAC99: The 36th ACM/IEEE-CAS/EDAC Design Automation Conference

June 21 - 25, 1999

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Cited By

View all

Jiang ZHu SHu JLi ZShi WHassoun S(2006)A new RLC buffer insertion algorithmProceedings of the 2006 IEEE/ACM international conference on Computer-aided design10.1145/1233501.1233614(553-557)Online publication date: 5-Nov-2006
https://dl.acm.org/doi/10.1145/1233501.1233614
Tsuchiya AHashimoto MOnodera HHirose F(2006)Interconnect RL extraction at a single representative frequencyProceedings of the 2006 Asia and South Pacific Design Automation Conference10.1145/1118299.1118424(515-520)Online publication date: 24-Jan-2006
https://dl.acm.org/doi/10.1145/1118299.1118424
Jiang ZHu SHu JLi ZShi W(2006)A New RLC Buffer Insertion Algorithm2006 IEEE/ACM International Conference on Computer Aided Design10.1109/ICCAD.2006.320173(553-557)Online publication date: Nov-2006
https://doi.org/10.1109/ICCAD.2006.320173
Mondal MMassoud Y(2005)Reducing pessimism in RLC delay estimation using an accurate analytical frequency dependent model for inductanceProceedings of the 2005 IEEE/ACM International conference on Computer-aided design10.5555/1129601.1129700(691-696)Online publication date: 31-May-2005
https://dl.acm.org/doi/10.5555/1129601.1129700
Mahmoud NGhoneima MIsmail YLach JQu GIsmail Y(2005)Physical limitations on the bit-rate of on-chip interconnectsProceedings of the 15th ACM Great Lakes symposium on VLSI10.1145/1057661.1057668(13-19)Online publication date: 17-Apr-2005
https://dl.acm.org/doi/10.1145/1057661.1057668
Kurokawa AYamamoto MOno NKage TInoue YMasuda H(2005)Capacitance and Yield Evaluations Using a 90-nm Process Technology Based on the Dense Power-Ground Interconnect ArchitectureProceedings of the 6th International Symposium on Quality of Electronic Design10.1109/ISQED.2005.29(153-158)Online publication date: 21-Mar-2005
https://dl.acm.org/doi/10.1109/ISQED.2005.29
Deodhar VDavis J(2005)Voltage Scaling, Wire Sizing and Repeater Insertion Design Rules for Wave-Pipelined VLSI Global Interconnect CircuitsProceedings of the 6th International Symposium on Quality of Electronic Design10.1109/ISQED.2005.128(592-597)Online publication date: 21-Mar-2005
https://dl.acm.org/doi/10.1109/ISQED.2005.128
Zheng LTenhunen H(2005)Wires as InterconnectsInterconnect-Centric Design for Advanced SoC and NoC10.1007/1-4020-7836-6_2(25-54)Online publication date: 2005
https://doi.org/10.1007/1-4020-7836-6_2
Kurokawa AOno NKage TMasuda HImai M(2004)DEPOGITProceedings of the 2004 Asia and South Pacific Design Automation Conference10.5555/1015090.1015218(517-522)Online publication date: 27-Jan-2004
https://dl.acm.org/doi/10.5555/1015090.1015218
Bin Liu Yici Cai Qiang Zhou Xianlong Hong (2004)Layer assignment algorithm for RLC crosstalk minimization2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)10.1109/ISCAS.2004.1329464(V-85-V-88)Online publication date: 2004
https://doi.org/10.1109/ISCAS.2004.1329464
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Recommendations

Effects of inductance on the propagation delay and repeater insertion in VLSI circuits

Thermal-aware methodology for repeater insertion in low-power VLSI circuits

Efficient interconnect design with novel repeater insertion for low power applications