research-article

Exploiting Idle Hardware to Provide Low Overhead Fault Tolerance for VLIW Processors

Authors:

Anderson L. Sartor,

Arthur F. Lorenzon,

Fernanda Kastensmidt,

Antonio C. S. BeckAuthors Info & Claims

ACM Journal on Emerging Technologies in Computing Systems (JETC), Volume 13, Issue 2

Article No.: 13, Pages 1 - 21

https://doi.org/10.1145/3001935

Published: 06 January 2017 Publication History

Abstract

Because of technology scaling, the soft error rate has been increasing in digital circuits, which affects system reliability. Therefore, modern processors, including VLIW architectures, must have means to mitigate such effects to guarantee reliable computing. In this scenario, our work proposes three low overhead fault tolerance approaches based on instruction duplication with zero latency detection, which uses a rollback mechanism to correct soft errors in the pipelanes of a configurable VLIW processor. The first uses idle issue slots within a period of time to execute extra instructions considering distinct application phases. The second works at a finer grain, adaptively exploiting idle functional units at run-time. However, some applications present high instruction-level parallelism (ILP), so the ability to provide fault tolerance is reduced: less functional units will be idle, decreasing the number of potential duplicated instructions. The third approach attacks this issue by dynamically reducing ILP according to a configurable threshold, increasing fault tolerance at the cost of performance. While the first two approaches achieve significant fault coverage with minimal area and power overhead for applications with low ILP, the latter improves fault tolerance with low performance degradation. All approaches are evaluated considering area, performance, power dissipation, and error coverage.

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Cited By

Condia JNarducci PSonza Reorda MSterpone L(2021)DYRE: a DYnamic REconfigurable solution to increase GPGPU’s reliabilityThe Journal of Supercomputing10.1007/s11227-021-03751-277:10(11625-11642)Online publication date: 1-Oct-2021
https://dl.acm.org/doi/10.1007/s11227-021-03751-2
Jost TNazar GCarro L(2020)SoMMA: A software-managed memory architecture for multi-issue processorsMicroprocessors and Microsystems10.1016/j.micpro.2020.10313977(103139)Online publication date: Oct-2020
https://doi.org/10.1016/j.micpro.2020.103139
Tonetto RCardoso DBrandalero MAgostini LNazar GAzambuja JBeck A(2019)A Knapsack Methodology for Hardware-based DMR Protection against Soft Errors in Superscalar Out-of-Order Processors2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC)10.1109/VLSI-SoC.2019.8920350(287-292)Online publication date: Oct-2019
https://doi.org/10.1109/VLSI-SoC.2019.8920350
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Index Terms

Exploiting Idle Hardware to Provide Low Overhead Fault Tolerance for VLIW Processors
1. Computer systems organization
  1. Dependable and fault-tolerant systems and networks
    1. Redundancy
    2. Reliability
2. Hardware
  1. Robustness
    1. Fault tolerance
      1. Error detection and error correction

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Published In

cover image ACM Journal on Emerging Technologies in Computing Systems

ACM Journal on Emerging Technologies in Computing Systems Volume 13, Issue 2

Special Issue on Nanoelectronic Circuit and System Design Methods for the Mobile Computing Era and Regular Papers

April 2017

377 pages

ISSN:1550-4832

EISSN:1550-4840

DOI:10.1145/3014160

Editor:
Yuan Xie
University of California, Santa Barbara, USA

Issue’s Table of Contents

Copyright © 2017 ACM.

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ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 06 January 2017

Accepted: 01 September 2016

Revised: 01 August 2016

Received: 01 September 2015

Published in JETC Volume 13, Issue 2

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Cited By

Condia JNarducci PSonza Reorda MSterpone L(2021)DYRE: a DYnamic REconfigurable solution to increase GPGPU’s reliabilityThe Journal of Supercomputing10.1007/s11227-021-03751-277:10(11625-11642)Online publication date: 1-Oct-2021
https://dl.acm.org/doi/10.1007/s11227-021-03751-2
Jost TNazar GCarro L(2020)SoMMA: A software-managed memory architecture for multi-issue processorsMicroprocessors and Microsystems10.1016/j.micpro.2020.10313977(103139)Online publication date: Oct-2020
https://doi.org/10.1016/j.micpro.2020.103139
Tonetto RCardoso DBrandalero MAgostini LNazar GAzambuja JBeck A(2019)A Knapsack Methodology for Hardware-based DMR Protection against Soft Errors in Superscalar Out-of-Order Processors2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC)10.1109/VLSI-SoC.2019.8920350(287-292)Online publication date: Oct-2019
https://doi.org/10.1109/VLSI-SoC.2019.8920350
Psiakis RKritikakou ASentieys OCasseau E(2019)Run-Time Coarse-Grained Hardware Mitigation for Multiple Faults on VLIW Processors2019 Conference on Design and Architectures for Signal and Image Processing (DASIP)10.1109/DASIP48288.2019.9049194(23-28)Online publication date: Oct-2019
https://doi.org/10.1109/DASIP48288.2019.9049194
Sartor ABecker PBeck A(2019)A fast and accurate hybrid fault injection platform for transient and permanent faultsDesign Automation for Embedded Systems10.1007/s10617-018-9217-023:1-2(3-19)Online publication date: 1-Jun-2019
https://dl.acm.org/doi/10.1007/s10617-018-9217-0
Sartor ABecker PHoozemans JWong SBeck A(2018)Dynamic Trade-off among Fault Tolerance, Energy Consumption, and Performance on a Multiple-Issue VLIW ProcessorIEEE Transactions on Multi-Scale Computing Systems10.1109/TMSCS.2017.27602994:3(327-339)Online publication date: 1-Jul-2018
https://doi.org/10.1109/TMSCS.2017.2760299
Erichsen ASartor ASouza JPereira MWong SBeck A(2018)ISA-DTMR: Selective Protection in Configurable Heterogeneous MulticoresApplied Reconfigurable Computing. Architectures, Tools, and Applications10.1007/978-3-319-78890-6_19(231-242)Online publication date: 8-Apr-2018
https://doi.org/10.1007/978-3-319-78890-6_19
Sartor ABecker PBeck A(2017)Simbah-FI: Simulation-Based Hybrid Fault Injector2017 VII Brazilian Symposium on Computing Systems Engineering (SBESC)10.1109/SBESC.2017.19(94-101)Online publication date: Dec-2017
https://doi.org/10.1109/SBESC.2017.19
Psiakis RKritikakou ASentieys O(2017)Run-time Instruction Replication for permanent and soft error mitigation in VLIW processors2017 15th IEEE International New Circuits and Systems Conference (NEWCAS)10.1109/NEWCAS.2017.8010170(321-324)Online publication date: Jul-2017
https://doi.org/10.1109/NEWCAS.2017.8010170
Psiakis RKritikakou ASentieys O(2017)NEDA: NOP Exploitation with Dependency Awareness for Reliable VLIW Processors2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI.2017.75(391-396)Online publication date: Jul-2017
https://doi.org/10.1109/ISVLSI.2017.75
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