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UMH: A Hardware-Based Unified Memory Hierarchy for Systems with Multiple Discrete GPUs

Authors:

Amir Kavyan Ziabari,

José L. Abellán,

David KaeliAuthors Info & Claims

ACM Transactions on Architecture and Code Optimization (TACO), Volume 13, Issue 4

Article No.: 35, Pages 1 - 25

https://doi.org/10.1145/2996190

Published: 02 December 2016 Publication History

Abstract

In this article, we describe how to ease memory management between a Central Processing Unit (CPU) and one or multiple discrete Graphic Processing Units (GPUs) by architecting a novel hardware-based Unified Memory Hierarchy (UMH). Adopting UMH, a GPU accesses the CPU memory only if it does not find its required data in the directories associated with its high-bandwidth memory, or the NMOESI coherency protocol limits the access to that data. Using UMH with NMOESI improves performance of a CPU-multiGPU system by at least 1.92 × in comparison to alternative software-based approaches. It also allows the CPU to access GPUs modified data by at least 13 × faster.

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Kamatar AFriese RGioiosa R(2023)A Task Based Approach for Co-Scheduling Ensemble Workloads on Heterogeneous Nodes2023 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)10.1109/IPDPSW59300.2023.00015(6-15)Online publication date: May-2023
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Belayneh LYe HChen KBlaauw DMudge TDreslinski RTalati NKloeckner AMoreira J(2022)Locality-Aware Optimizations for Improving Remote Memory Latency in Multi-GPU SystemsProceedings of the International Conference on Parallel Architectures and Compilation Techniques10.1145/3559009.3569649(304-316)Online publication date: 8-Oct-2022
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Index Terms

UMH: A Hardware-Based Unified Memory Hierarchy for Systems with Multiple Discrete GPUs
1. Computer systems organization
  1. Architectures
    1. Other architectures
      1. Heterogeneous (hybrid) systems
2. Hardware
  1. Integrated circuits

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Published In

cover image ACM Transactions on Architecture and Code Optimization

ACM Transactions on Architecture and Code Optimization Volume 13, Issue 4

December 2016

648 pages

ISSN:1544-3566

EISSN:1544-3973

DOI:10.1145/3012405

Editor:
Koen De Bosschere
Ghent University

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Copyright © 2016 ACM.

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Publication History

Published: 02 December 2016

Accepted: 01 September 2016

Revised: 01 August 2016

Received: 01 May 2016

Published in TACO Volume 13, Issue 4

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Cited By

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Belayneh LYe HChen KBlaauw DMudge TDreslinski RTalati NKloeckner AMoreira J(2022)Locality-Aware Optimizations for Improving Remote Memory Latency in Multi-GPU SystemsProceedings of the International Conference on Parallel Architectures and Compilation Techniques10.1145/3559009.3569649(304-316)Online publication date: 8-Oct-2022
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Yao CLiu WTang WHu S(2022)EAISFuture Generation Computer Systems10.1016/j.future.2022.01.004130:C(253-268)Online publication date: 1-May-2022
https://dl.acm.org/doi/10.1016/j.future.2022.01.004
Kalkhof TKoch A(2021)Efficient Physical Page Migrations in Shared Virtual Memory Reconfigurable Computing Systems2021 International Conference on Field-Programmable Technology (ICFPT)10.1109/ICFPT52863.2021.9609831(1-10)Online publication date: 6-Dec-2021
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Baruah TSun YDincer AMojumder SAbellan JUkidave YJoshi ARubin NKim JKaeli D(2020)Griffin: Hardware-Software Support for Efficient Page Migration in Multi-GPU Systems2020 IEEE International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA47549.2020.00055(596-609)Online publication date: Feb-2020
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Sun YBaruah TMojumder SDong SGong XTreadway SBao YHance SMcCardwell CZhao VBarclay HZiabari AChen ZUbal RAbellán JKim JJoshi AKaeli DManne SHunter HAltman E(2019)MGPUSimProceedings of the 46th International Symposium on Computer Architecture10.1145/3307650.3322230(197-209)Online publication date: 22-Jun-2019
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