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Exploiting spatial locality in data caches using spatial footprints

Authors:

Christopher WilkersonAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 26, Issue 3

Pages 357 - 368

https://doi.org/10.1145/279361.279404

Published: 16 April 1998 Publication History

Abstract

Modern cache designs exploit spatial locality by fetching large blocks of data called cache lines on a cache miss. Subsequent references to words within the same cache line result in cache hits. Although this approach benefits from spatial locality, less than half of the data brought into the cache gets used before eviction. The unused portion of the cache line negatively impacts performance by wasting bandwidth and polluting the cache by replacing potentially useful data that would otherwise remain in the cache.This paper describes an alternative approach to exploit spatial locality available in data caches. On a cache miss, our mechanism, called Spatial Footprint Predictor (SFP), predicts which portions of a cache block will get used before getting evicted. The high accuracy of the predictor allows us to exploit spatial locality exhibited in larger blocks of data yielding better miss ratios without significantly impacting the memory access latencies. Our evaluation of this mechanism shows that the miss rate of the cache is improved, on average, by 18% in addition to a significant reduction in the bandwidth requirement.

References

[1]

S. G. Abraham, R. A. Sugumar, D. Windheiser, B. R. Rau, and R. Gupta. Predictability of load/store instruction latencies. In Proceedings of the 26th Annual International Symposium on Microarchitecture, pages 139-152, Austin, Texas, December 1-3, 1993.

Digital Library

[2]

J.-L. Baer and T.-F. Chen. An effective on-chip preloading chip scheme to reduce data access penalty, in Proceedings of Supercomputing, 1991.

Digital Library

[3]

K. Bolland and A. Dollas. Predicting and precluding problems with memory latency. In IEEE Micro, pages 59-66, August, 1994.

Digital Library

[4]

D. Burger, J. R. Goodman, and A. Kfigi. Memory bandwidth limitations of future microprocessors. In Proceedings of the 23rd Annual International Symposium on Computer Architecture, pages 78-89, Philadelphia, PA, May 22-24, 1996.

Digital Library

[5]

W. Y. Chen, A. A. Mahlke, P. P. Chang, and W. W. Hwu. Data access microarchitectures for superscalar processors with compiler-assisted data prefetching. In Proceedings of Microcomputing 24, 1991.

Digital Library

[6]

A. Gonz~ilez, C. Aliagas, and M. Valero. A data cache with multiple caching strategies tuned to different types of locality. In Proceedings of International Conference on Supercomputing, pages 338-347, Barcelona, Spain, July, 1995.

Digital Library

[7]

T. Johnson, M. Merten, and W. mei W. Hwu. Run-time spatial locality detection and optimization. In Proceedings of the 30th Annual International Symposium on Microarchitecture, pages 57-64, Research Triangle Park, NC, 1997.

Digital Library

[8]

T. L. Johnson and W. mei W. Hwu. Run-time adaptive cache hierarchy management via reference analysis. In Proceedings of the 24rd Annual International Symposium on Computer Architecture, pages 315-326, Denver, Colorado, 1997.

Digital Library

[9]

N. P. Jouppi. Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers. In Proceedings of the 17th Annual International Symposium on Computer Architecture, pages 364- 373, Seattle, Washington, May 28-31, 1990.

Digital Library

[10]

M. H. Lipasti, W. J. Schmidt, S. R. Kunkel, and R. R. Roediger. SPAID: Software prefetching in pointer- and callintensive environments. In Proceedings of the 28th Annual International Symposium on Microarchitecture, pages 231- 236, Ann Arbor, Michigan, 1995.

Digital Library

[11]

L. Liu. Cache designs with partial address matching. In Proceedings of the 27th Annual International Symposium on Microarchitecture, pages 128-136, San Jose, California, November 30-December 2, 1994.

Digital Library

[12]

C.-K. Luk and T. C. Mowry. Compiler-based prefetching for recursive data structures. In Proceedings of the Seventh International Conference on Architectural Support for Programming Languages and Operating Systems, pages 222- 233, Cambridge, MA, October 1-5, 1996.

Digital Library

[13]

T. C. Mowry, M. S. Lam, and A. Gupta. Design and evaluation of a compiler algorithm for prefetching. In Proceedings of the Fifth International Conference on Architectural Support for Programming Languages and Operating Systems, pages 62-73, Boston, Massachusetts, October 12-15, 1992.

Digital Library

[14]

S. Przybylski. The performance impact of block sizes and fetch strategies. In Proceedings of the 17th Annual International Symposium on Computer Architecture, pages 160- 169, Seattle, Washington, May 28-31, 1990.

Digital Library

[15]

A. Seznec. Decoupled sectored caches: Conciliating low tag implementation cost and low miss ratio. In Proceedings of the 21st Annual International Symposium on Computer Architecture, pages 384-393, Chicago, IL, April, 1994.

Digital Library

[16]

A.J. Smith. Cache memories. In Computing Surveys, pages 473-530, vol. 14, no. 3, 1982.

Digital Library

[17]

A. J. Smith. Line (block) size choice for cpu cache memories. In IEEE Transactions on Computers, pages 1063-1075, vol. C-36, 1987.

Digital Library

[18]

G. Tyson, M. Farrens, J. Matthews, and A. R. Pleszkun. A modified approach to data cache management. In Proceedings of the 28th Annual International Symposium on Microarchitecture, pages 93-103, Ann Arbor, Michigan, 1995.

Digital Library

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Exploiting spatial locality in data caches using spatial footprints

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Information

Published In

cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 26, Issue 3

Special Issue: Proceedings of the 25th annual international symposium on Computer architecture (ISCA '98)

June 1998

379 pages

ISSN:0163-5964

DOI:10.1145/279361

Chairmen:
Mateo Valero
Univ. Politecnica de Catalunya, Barcelona, Spain
,
Gurindar S. Sohi
Univ. of Wisconsin-Madison, Madison
,
Editor:
Doug DeGroot

Issue’s Table of Contents

ISCA '98: Proceedings of the 25th annual international symposium on Computer architecture
April 1998
402 pages
ISBN:0818684917
Chairmen:
Mateo Valero
Univ. Politecnica de Catalunya
,
Gurindar S. Sohi
Univ. of Wisconsin-Madison, Madison
,
Editor:
Doug DeGroot

Copyright © 1998 Authors.

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 16 April 1998

Published in SIGARCH Volume 26, Issue 3

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https://doi.org/10.1145/3673653
Bera RRanganathan ARakshit JMahto SNori AGaur JOlgun AKanellopoulos KSadrosadati MSubramoney SMutlu O(2024)Constable: Improving Performance and Power Efficiency by Safely Eliminating Load Instruction Execution2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA)10.1109/ISCA59077.2024.00017(88-102)Online publication date: 29-Jun-2024
https://doi.org/10.1109/ISCA59077.2024.00017
Zhang PKannan RNori APrasanna V(2024)Accelerating Graph Analytics Using Attention-Based Data PrefetcherSN Computer Science10.1007/s42979-024-02989-w5:5Online publication date: 13-Jun-2024
https://doi.org/10.1007/s42979-024-02989-w
Wu HNathella KPabst MSunwoo DJain ALin C(2022)Practical Temporal Prefetching With Compressed On-Chip MetadataIEEE Transactions on Computers10.1109/TC.2021.306590971:11(2858-2871)Online publication date: 1-Nov-2022
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Lal SVarma BJuurlink B(2022)A Quantitative Study of Locality in GPU Caches for Memory-Divergent WorkloadsInternational Journal of Parallel Programming10.1007/s10766-022-00729-250:2(189-216)Online publication date: 5-Apr-2022
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