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Power-conscious high level synthesis using loop folding

Authors:

Daehong Kim,

Kiyoung ChoiAuthors Info & Claims

DAC '97: Proceedings of the 34th annual Design Automation Conference

Pages 441 - 445

https://doi.org/10.1145/266021.266194

Published: 13 June 1997 Publication History

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Abstract

In this paper, a transformation technique, called power-consciousloop folding is proposed for high level synthesis of alow power system. Our work is focused on reducing the powerconsumed by functional units through the decrease of switchingactivity in a data path dominated circuit containing loops. Thetransformation algorithm has been implemented and integratedinto a high level synthesis system for experiments. In ourexperiments, we could achieve power reduction of up to 50% forcircuits dominated by functional units.

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Reddy SShahabadkar RMamatha CChatterjee P(2017)Protection policy in networked locations using machine learning and data science approach2017 3rd International Conference on Applied and Theoretical Computing and Communication Technology (iCATccT)10.1109/ICATCCT.2017.8389140(237-240)Online publication date: Dec-2017
https://doi.org/10.1109/ICATCCT.2017.8389140
Lamoureux JLemieux GWilton S(2008)GlitchLessIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.200123716:11(1521-1534)Online publication date: 1-Nov-2008
https://dl.acm.org/doi/10.1109/TVLSI.2008.2001237
Vamos ARencz M(2008)FPGA power model for minimizing the thermal dissipation2008 14th International Workshop on Thermal Inveatigation of ICs and Systems10.1109/THERMINIC.2008.4669897(148-151)Online publication date: Sep-2008
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Power-conscious high level synthesis using loop folding

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Published In

DAC '97: Proceedings of the 34th annual Design Automation Conference

June 1997

788 pages

ISBN:0897919203

DOI:10.1145/266021

Chairmen:
Ellen J. Yoffa
IBM T. J. Watson Research Center, Yorktown Heights, NY
,
Giovanni De Micheli
Stanford Univ., Stanford, CA
,
Jan M. Rabaey
Univ. of California, Berkeley

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 13 June 1997

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DAC97: The 34th Design Automation Conference

June 9 - 13, 1997

California, Anaheim, USA

Acceptance Rates

DAC '97 Paper Acceptance Rate 139 of 400 submissions, 35%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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62nd ACM/IEEE Design Automation Conference

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Reddy SShahabadkar RMamatha CChatterjee P(2017)Protection policy in networked locations using machine learning and data science approach2017 3rd International Conference on Applied and Theoretical Computing and Communication Technology (iCATccT)10.1109/ICATCCT.2017.8389140(237-240)Online publication date: Dec-2017
https://doi.org/10.1109/ICATCCT.2017.8389140
Lamoureux JLemieux GWilton S(2008)GlitchLessIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.200123716:11(1521-1534)Online publication date: 1-Nov-2008
https://dl.acm.org/doi/10.1109/TVLSI.2008.2001237
Vamos ARencz M(2008)FPGA power model for minimizing the thermal dissipation2008 14th International Workshop on Thermal Inveatigation of ICs and Systems10.1109/THERMINIC.2008.4669897(148-151)Online publication date: Sep-2008
https://doi.org/10.1109/THERMINIC.2008.4669897
Lamoureux JLemieux GWilton SDeHon AHutton M(2007)GlitchLessProceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays10.1145/1216919.1216946(156-165)Online publication date: 18-Feb-2007
https://dl.acm.org/doi/10.1145/1216919.1216946
Macii EPedram MSomenzi F(2006)High-level power modeling, estimation, and optimizationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.73618117:11(1061-1079)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.736181
Kim DShin DChoi K(2005)Pipelining with common operands for power-efficient linear systemsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2005.85714613:9(1023-1034)Online publication date: 1-Sep-2005
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Muthukumar VRadhakrishnan BSelvaraj H(2005)Multiple voltage and frequency scheduling for power minimizationJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2004.07.00551:6-7(382-394)Online publication date: 1-Jun-2005
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Wilton SAng SLuk W(2004)The Impact of Pipelining on Energy per Operation in Field-Programmable Gate ArraysField Programmable Logic and Application10.1007/978-3-540-30117-2_73(719-728)Online publication date: 2004
https://doi.org/10.1007/978-3-540-30117-2_73
Abddollahi APedarm MFallah FGhosh I(2003)Precomputation-based guarding for dynamic and leakage power reductionProceedings 21st International Conference on Computer Design10.1109/ICCD.2003.1240878(90-97)Online publication date: 2003
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Radhakrishnan BVenkatesan M(2003)Multiple voltage and frequency scheduling for power minimizationEuromicro Symposium on Digital System Design, 2003. Proceedings.10.1109/DSD.2003.1231949(279-284)Online publication date: 2003
https://doi.org/10.1109/DSD.2003.1231949
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Power management in high-level synthesis

Interconnect-aware low-power high-level synthesis

Transient power management through high level synthesis

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Power management in high-level synthesis

Interconnect-aware low-power high-level synthesis

Transient power management through high level synthesis

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