Efficient testing of clock regenerator circuits in scan designs

This paper presents H-SCAN, a practical testing methodology that can be easily applied to a high-level design specification. H-SCAN allows the use of combinational test patterns without the high area and test application time overheads associated with ...

Software-based self-test (SBST) has recently emerged as an effective methodology for the manufacturing test of embedded processors in SoCs. SBST is a nonintrusive approach that has the potential to provide high-quality at-speed testing at virtually zero ...

Abstract: Existing flip-flop selection and test generation methods for partial scan designs assume the use of a separate scan clock. With a separate clock for the scan operation, the states of the non-scan flip-flops can be frozen during the scan ...