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Modelling and mitigation of time-zero variability in sub-16nm finfet-based STT-MRAM memories

Authors:

Liesbet Van Der Perre,

Wim DehaeneAuthors Info & Claims

GLSVLSI '14: Proceedings of the 24th edition of the great lakes symposium on VLSI

Pages 243 - 244

https://doi.org/10.1145/2591513.2591573

Published: 20 May 2014 Publication History

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Abstract

Spin-transfer torque magnetic RAM (STT-MRAM) is one of the most promising non-volatile memory technologies and shows potential as an SRAM replacement. However, targeted for advanced CMOS technologies such as the 14nm FinFET node, time-zero variability is a major concern for these memory technologies. In this paper, we investigate the STT-MRAM variability with respect to different technology scenarios. We show the impact of these variations on the bit error rate of the emerging STT-MRAM memories.

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K.J. Kuhn et al. Process technology variation. 2011.

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Y. Wang et al. A 4.0-ghz 291-mb voltage-scalable sram design in 32-nm high-k metal-gate cmos with integrated power management. 2009.

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Chih-Hsiang Ho et al. A physics-based statistical model for reliability of stt-mram considering oxide variability. 2013.

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Y. Emre et al. Enhancing the reliability of stt-ram through circuit and system level techniques. 2012.

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Index Terms

Modelling and mitigation of time-zero variability in sub-16nm finfet-based STT-MRAM memories
1. Hardware
  1. Hardware test
    1. Memory test and repair

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Published In

GLSVLSI '14: Proceedings of the 24th edition of the great lakes symposium on VLSI

May 2014

376 pages

ISBN:9781450328166

DOI:10.1145/2591513

General Chairs:
Joseph R. Cavallaro
Rice University, USA
,
Tong Zhang
Rensselaer Polytechnic Inst., USA
,
Program Chairs:
Alex K. Jones
University of Pittsburgh, USA
,
Hai (Helen) Li
University of Pittsburgh, USA

Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for third-party components of this work must be honored. For all other uses, contact the Owner/Author.

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Association for Computing Machinery

New York, NY, United States

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Published: 20 May 2014

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SIGDA

GLSVLSI '14: Great Lakes Symposium on VLSI 2014

May 21 - 23, 2014

Texas, Houston, USA

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GLSVLSI '14 Paper Acceptance Rate 49 of 179 submissions, 27%;

Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Abstract

References

Index Terms

Recommendations

Write-optimized reliable design of STT MRAM

Advanced Low Power Spintronic Memories beyond STT-MRAM

STT-MRAM-Based PUF Architecture Exploiting Magnetic Tunnel Junction Fabrication-Induced Variability

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