research-article

Explicit reservation of cache memory in a predictable, preemptive multitasking real-time system

Authors:

Neil C. Audsley,

Robert I. DavisAuthors Info & Claims

ACM Transactions on Embedded Computing Systems (TECS), Volume 13, Issue 4s

Article No.: 120, Pages 1 - 25

https://doi.org/10.1145/2523070

Published: 01 April 2014 Publication History

Abstract

We describe and evaluate explicit reservation of cache memory to reduce the cache-related preemption delay (CRPD) observed when tasks share a cache in a preemptive multitasking hard real-time system. We demonstrate the approach using measurements obtained from a hardware prototype, and present schedulability analyses for systems that share a cache by explicit reservation. These analyses form the basis for a series of experiments to further evaluate the approach. We find that explicit reservation is most useful for larger task sets with high utilization. Some task sets cannot be scheduled with a conventional cache, but are schedulable with explicit reservation.

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Cited By

Kloda TGracioli GTabish RMirosanlou RMancuso RPellizzoni RCaccamo M(2023)Lazy Load Scheduling for Mixed-criticality Applications in Heterogeneous MPSoCsACM Transactions on Embedded Computing Systems10.1145/358769422:3(1-26)Online publication date: 13-May-2023
https://dl.acm.org/doi/10.1145/3587694
Koo CKim H(2018)Measurement of Cache-Related Preemption Delay for Spacecraft Computers2018 IEEE 24th International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA)10.1109/RTCSA.2018.00037(234-235)Online publication date: Aug-2018
https://doi.org/10.1109/RTCSA.2018.00037
Davis RAltmeyer SBurns A(2018)Mixed Criticality Systems with Varying Context Switch Costs2018 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)10.1109/RTAS.2018.00024(140-151)Online publication date: Apr-2018
https://doi.org/10.1109/RTAS.2018.00024
Show More Cited By

Index Terms

Explicit reservation of cache memory in a predictable, preemptive multitasking real-time system
1. Computer systems organization
  1. Embedded and cyber-physical systems
  2. Real-time systems
2. Hardware
  1. Integrated circuits
    1. Semiconductor memory
      1. Dynamic memory

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Published In

cover image ACM Transactions on Embedded Computing Systems

ACM Transactions on Embedded Computing Systems Volume 13, Issue 4s

Special Issue on Real-Time and Embedded Technology and Applications, Domain-Specific Multicore Computing, Cross-Layer Dependable Embedded Systems, and Application of Concurrency to System Design (ACSD'13)

July 2014

571 pages

ISSN:1539-9087

EISSN:1558-3465

DOI:10.1145/2601432

Editors:
Sandeep K. Shukla
Virginia Tech, USA
,
Josep Carmona
Universitat Politècnica de Catalunya, Spain
,
Mihai Teodor Lazarescu
Politecnico di Torino, Italy
,
Marta Pietkiewicz-koutny
Newcastle University, UK

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Copyright © 2014 ACM.

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Association for Computing Machinery

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ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 01 April 2014

Accepted: 01 August 2013

Revised: 01 February 2013

Received: 01 June 2012

Published in TECS Volume 13, Issue 4s

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Cited By

Kloda TGracioli GTabish RMirosanlou RMancuso RPellizzoni RCaccamo M(2023)Lazy Load Scheduling for Mixed-criticality Applications in Heterogeneous MPSoCsACM Transactions on Embedded Computing Systems10.1145/358769422:3(1-26)Online publication date: 13-May-2023
https://dl.acm.org/doi/10.1145/3587694
Koo CKim H(2018)Measurement of Cache-Related Preemption Delay for Spacecraft Computers2018 IEEE 24th International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA)10.1109/RTCSA.2018.00037(234-235)Online publication date: Aug-2018
https://doi.org/10.1109/RTCSA.2018.00037
Davis RAltmeyer SBurns A(2018)Mixed Criticality Systems with Varying Context Switch Costs2018 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)10.1109/RTAS.2018.00024(140-151)Online publication date: Apr-2018
https://doi.org/10.1109/RTAS.2018.00024
Davis RAltmeyer SIndrusiak LMaiza CNelis VReineke J(2018)An extensible framework for multicore response time analysisReal-Time Systems10.1007/s11241-017-9285-454:3(607-661)Online publication date: 1-Jul-2018
https://dl.acm.org/doi/10.1007/s11241-017-9285-4
Shahid AKhalid BQadri MQadri NAhmed J(2016)Design Space Exploration Using Cycle Accurate SimulatorInnovative Research and Applications in Next-Generation High Performance Computing10.4018/978-1-5225-0287-6.ch004(66-79)Online publication date: 2016
https://doi.org/10.4018/978-1-5225-0287-6.ch004
Panda PPatil GRaveendran B(2016)A survey on replacement strategies in cache memory for embedded systems2016 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER)10.1109/DISCOVER.2016.7806218(12-17)Online publication date: Aug-2016
https://doi.org/10.1109/DISCOVER.2016.7806218
Kafshdooz MEjlali A(2015)Dynamic Shared SPM Reuse for Real-Time Multicore Embedded SystemsACM Transactions on Architecture and Code Optimization10.1145/273805112:2(1-25)Online publication date: 11-May-2015
https://dl.acm.org/doi/10.1145/2738051
Lofwenmark ANadjm-Tehrani S(2015)Experience reportProceedings of the 2015 IEEE 26th International Symposium on Software Reliability Engineering (ISSRE)10.1109/ISSRE.2015.7381809(153-160)Online publication date: 2-Nov-2015
https://dl.acm.org/doi/10.1109/ISSRE.2015.7381809

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